Ramya Mohan

**** ******** *****,

Apartment #****,

Sunnyvale,

CA – 94085

Email: y75dfl@r.postjobfree.com

Ph: 408-***-****

Objective

Seeking a position in DSP Design and Development for Wireless Communications

Experience

8 years of experience in the field of Digital Signal Processing, Wireless Communications and Embedded Technologies.

Aug 2007- Present Lead Engineer, WCDMA NodeB-L1, Alcatel Lucent Technologies

Oct 2006- July 2007 Senior Software Engineer, Next Generation Networks, Kyocera Wireless India, Bangalore

Feb 2004 –Oct 2006 Senior Systems Engineer, Wireless Group, Accord Software & Systems, Bangalore

Aug 2002 – Jan 2004 DSP Engineer, Brandwidth Technologies, Bangalore

Skill Set

Wireless Technology WCDMA-NodeB Physical Layer for UMTS releases 6&8.

Worked on the implementation and development of CDMA based baseband receivers

Platforms TI Processors TMS320C6487, C64/2x, C5x family

Programming Tools Code Composer Studio, Metrowerks Code Warrior

Programming Languages C, Assembly on the TI 6x, 5x processors

Training Agile Development & SCRUM Methodologies

Highlights Received appreciation for debugging a complex cache related issue inherent to the TCI64x+ processor

during Global Pre-Integration for the V6 release of UMTS.

Recipient of the “On the Spot Recognition - Night Out Award” for providing support and fixing a

failing Priority-0 Test case during Global Pre-Integration of the V8 release of UMTS

PROFESSIONAL EXPERIENCE

Aug 2007- Present

Lead Engineer, WCDMA NodeB-L1

Alcatel-Lucent Technologies, Bangalore, India

•Feature 89411 for UMTS Release 8 –Aggregate HSPA throughput increase for the eCEM (Enhanced Channel Element Module)

Team Size: 6.This feature was implemented in the SCRUM development model

Duration: 1 Yr 1 Month

Feature requirement

The feature required peak DL and UL throughputs of 61.2 Mbps and 31.2 Mbps.The existent throughputs per board were 28 Mbps in

downlink and 10 Mbps in uplink.

The eCEM releases V6 and V7 have been implemented using only one of the three cores of the TCI6487 processor. In order to aid

better UL throughput in terms of MIPS, Phase 1 of the 89411 feature aimed at a core split, whereby the messaging to the host

& EDCH processing are handled by Core-0 and the HSDPA processing by Core-2.Also, on the uplink, the Turbo Decoding process

was being done by a coprocessor of the DSP, whose throughput was limited to 15 Mbps. The current UL Turbo (TCC) decoder in

the DSP was replaced by compatible TCC decoder(s) in the FPGA.

The limiting factor on the downlink was the HSSL link between the Controller and the Modem; this was overcome by replacing

the link with Ethernet.

Role

Feature Owner for the 89411- feature and first POC for Global Pre-Integration and Field Issues. Involved in coding, design

and testing the code churned out per Sprint Cycle. Involved in fixing issues and providing enhancements during Board Level

Testing, Board Pre-integration, and System Testing.

•Feature w85011 for UMTS release 6

Team Size: 8

Duration: February 2008 – February 2010(2 Yrs)

Feature Requirement

This feature involved the migration of the DSP code from an “xCEM” to an “eCEM” platform. The changes in the feature were

platform intensive. Internal interconnection is based on sRIO rather than PCI. The Digital signal processor sub-system is

built around a Texas instrument Faraday, namely the TCI6487, which can operate at 1.2GHz as compared to the TCI6416 (xCEM)

whose maximum is at 850MHz.The eCEM allows the DSP to embed three (3) processing cores and 3 MB of internal memory.

Role

Module owner for the EXEC block (Board boot-up, Peripheral Initializations(SRIO,PLL,Timers,FSYNC,EDMA)).Involved in the code

reviews for the remaining blocks i.e Interface blocks to the Host and the FPGA’s, Error Monitoring, Uplink and Downlink

EDCH,involved in resolving issues and proving support during DSP Integration Testing, Board Level Testing & Board

Pre-Integration.

Oct 2006- July 2007

Senior Software Engineer,

Kyocera Wireless India, Bangalore

•Next Generation Networks

Team Size: 15

Duration: December 2006- July 2007

The PHS (Personal Handyphone System) consists of a Channel Card containing two 8126 QUAD DSP’s and a PQIII processor.

Frequency Domain and User Domain Processing and the MAC run on the Channel card and the Time domain processing runs on the

TDP card and the FPGA.

Role

Involved in debugging and analyzing the coarse time estimation module, Profile Estimation and Optimization for User Domain

Processing and Frequency Domain Processing

Feb 2004- Oct 2006

Senior Systems Engineer, Wireless Group

Accord Software & Systems, Bangalore

•2-Channel CDMA receiver

Client: RCI, India

Team Size: 4

Duration: 9 Months

The CDMA receiver incorporates features of correlation, signal acquisition and tracking, data demodulation at a bit rate of

9600 baud. It consists of the TMS320C6416 as the master and is interfaced to a Flash, UART, FIFO, ADC and the Bus Unit. The

system uses the MIL1553B protocol to output the channel data along with an RS422 Interface. The RS232 interface provides the

host to target communication for real time debugging.

Role

Was involved in the software design, implementation and debugging of the receiver, involved in the design and implementation

of a secondary boot loading feature in TMS320C64x assembly to load the application code into the DSP RAM

•4 – Channel GPS based receiver

Team Size: 4

Duration: 10 Months

The GPS based receiver incorporates an FPGA based correlator, with the DSP providing timing synchronization, carrier

recovery, code recovery, Bit Synchronization and Data Extraction at a data rate of 50 bps.The system consists of the

TMS320C5509 as the master and is interfaced to an FPGA, Dual ADC’s, Flash and a UART. The system uses the MIL1553B protocol

to output the channel data along with an RS422 Interface.

Role

Was involved in the software design, implementation and bring up of the subsystem and resolving interface issues between the

devices

•2 Channel CDMA Receiver

Team Size: 1

Duration: 8 months

The CDMA receiver extracts data from a single channel Direct Sequence Spread Spectrum and a BPSK modulated signal. It

incorporates an FPGA based correlator, with the DSP providing timing synchronization, carrier recovery, code recovery, Bit

synchronization and Data Extraction at 4000 baud. The system comprises of a TMS320C6416 processor as the master and is

interfaced to an FPGA, Flash, UART and an ADC.

Role

Involved in the hardware design of the sub-system, preparation of schematics and review of the routed PCB and the Gerbers for

the PCB. Involved in the re-design of the software for a more modular approach, responsibility included software and hardware

re-design, implementation, real time debugging of the receiver, subsequent delivery and testing of the board to the customer.

Aug 2002- Jan 2004

DSP Engineer

Brandwidth Technologies, Bangalore

•Implementation and Optimization of G.729A Encoder and Decoder on TMS320C6201

Client: Central Research Laboratory, Bharat Electronics, Bangalore

The G.729 speech codec uses the conjugate-structure algebraic code excited linear-prediction (CS-ACELP) algorithm, which is

an analysis-by-synthesis algorithm and belongs to the class of speech coding algorithms known as code excited linear

prediction (CELP). The G.729A is the annex A for G.729 to reduce the complexity of the CS-ACELP speech codec.

Role

To optimize the performance of the vocoder, integrate and test the implemented algorithm

EDUCATION

Bachelors in Electronics and Communication Engineering from the Bangalore University, 2001

Contact this candidate