Engineer Design
Resume:
Vijayalakshmi Kannappan
Columbus, Ohio,
United States - 43220
Phone No: 001-614-***-**** E-mail: xrg610@r.postjobfree.com
xrg610@r.postjobfree.com
CAREER OBJECTIVE:
To establish myself as The Best Design Engineer in High speed, HDI, RF, Mixed signal, Power supply designs, ATE boards and IC package design.
RESUME SUMMARY:
4 years of total experience in PCB Design using various EDA tools.
- 3.5 years of experience in PCB design
- 6 months of experience in IC package design
In depth working knowledge of High Speed PCB designs and ATE, DFM and DFT consideration at PCB level.
Expertise in technologies like DDR, QDR, PCIe, Ethernet, SATA, SERDES etc.
Undergone training for High speed and HDI designs and PCB Manufacturing Process.
Imparting training on High Speed Designs.
Mentor for new team members.
EXPERIENCE SUMMARY:
Organization : Tessolve Services Pvt Ltd., Coimbatore.
Period : Aug 2006 – Jul 2010
Designation : Sr.Design Engineer
TECHNICAL SKILL SET:
EDA Tools
Cadence Allegro 15.x, 16.x, Concept HDL, Cadence APD 620 and OrCAD Capture.
CAM Tools
CAM 9.5
Drafting Tools
ACAD 2002
RESPONSIBILITIES:
Schematic symbol creation
Schematic creation
Parts Library Creation
Major & Discrete components Placement
Impedance calculation & Constraint setting
Signal grouping and classification
Power plane segmentation and via dropping
Clock Signal Routing
Critical Signal Routing and Differential pair Routing
Length matching
Single Ended Traces routing
Error checking, Layer biasing and Cleanup
Test Coupons creation (As per requirement)
Post processing & Internal Auditing
Gerber files generation
Netlist verification and editing Gerber files using CAM350
PCB fabrication package creation
PCB component assembly package creation
PROJECTS HANDLED:
1. Role : Design Engineer.
Duration : 7 Weeks
Board title : DM648
Platform : Allegro 15.7.
The design comprises of a core processor as its main device. The processor supports two 256 MB SDRAMs with DDR2 technology and a flash memory. The processor has two external interfaces using Combo connector.
Board complexity:
Design has 3 different impedance requirements like 50, 60 and 100 ohm with 10 layer stack-up. The DDR signals were grouped into address, data and command & control and routed with ‘Tree’ Topology from processor to memory. Signals crossing the splits were avoided. Length matching was done according to the DDR2 Guidelines. Terminations for DDR signals and proper decoupling and Plane area are provided for power supplies.
2. Role : Design Engineer.
Duration : 10 Weeks
Board title : MCD CARD
Platform : Allegro 16.0.
It is a Communication board consists of AMCC PPC460GT I/O processor, FPGA, MachXO CPLD, SoDIMM, RF section, 10/100/1000 Base-T Gigabit Transceivers, Gigabit Ethernet (Magnetics), Wideband LNA, PSK/QPSK Satellite Tuner ICs and Advanced Dual Demodulators used for Satellite digital TV/ Set-Top Boxes. The I/O processor is interfaced to a 1Gb DDR2 SO-DIMM memory module.
Board complexity:
Design has 4 different impedance requirements like 50, 75,100,150 Ohm with 12 layer stack-up. DDR2 signals were grouped into Data, Address, Command and Control and routed byte wise in different layers to avoid crosstalk. Signals crossing the splits were avoided. Length matching was done according to the DDR2 Guidelines. Terminations for DDR signals and proper decoupling and Plane area are provided for power supplies. Post route analysis was done and found good.
3. Role : Design Engineer.
Duration : 6 Weeks
Board title : DDVDR.
Platform : Allegro 15.7
The DVR card is basically a digital Video Recording box based on the DM6446 digital media SoC from TI. DVR card supports single DVD drive configuration. The DVD drive can be controlled by either the Back End Processor or the on-board processor.
Board complexity:
The board was designed for 12 layers. The design had more than 900 components and 1000 signals. The design has DDR2, SATA and USB signals routed with layer restrictions. Proper reference has been provided for all the critical signals. Signal flow and Delay Matching between Processor, Boot FLASH and FPGA were done as per the requirements. The design has 50 ohm, 100ohm differential and 75 ohm signals.
4. Role : Design Engineer.
Duration : 6 Weeks
Board title : Video Board.
Platform : Allegro 15.7.
The board comprises of a Processor with 2 SDRAM with DDR2 technology and a flash memory and connectors. This board is designed to plug in to a main carrier board which will provide further interfacing to items such as UARTS or other processors. This board is based on the DM642 Evaluation Module from Spectrum digital.
Board complexity:
The board was designed with 80 mil thickness and with 10 layers. All the components were chosen with ROHS compliance. The component placement was critical. The signals were grouped and length matching was done considering the Manhattan length of each signal group. The signal from processor to the connector through termination resistor and memory were matched separately. Decoupling capacitor requirement and proper plane area for power supplies were considered and followed.
5. Role : Design Engineer.
Duration : 5 Weeks
Board title : DL1 MK3
Platform : Allegro 15.7.
The board comprises GPS module from Ublox LEA-4T, Texas Instrument's Digital Signal Controller, USB connector, DC-DC converters and Analog section.
Board complexity:
The board is designed with 8 layer stackup & to satisfy 50, 90 & 100 ohm impedance requirements. RF signal of the GPS module is routed in “Coplanar waveguide with ground” structure and the entire board under the RF section in void of other traces and planes. Proper care has been taken to isolate the sensitive traces like USB from crystal signals. High current Switching regulator's placement & routing were done as per the Guidelines. Power plane segmentation is done to match both the requirements of current carrying & reference to critical signal.
ATE knowledge:
Hand on experience in ATE boards like
Integraflex
HP93K
Cypress IST sort & TT boards
Ultraflex
LTX Fusion
* designed both probe cards and dut boards.
IC Package Design
Hand on experience in both wire bond & flip chip designs.
ACADEMIC PROFILE:
Degree : Bachelor of Engineering in Electrical & Electronics Engineering
Year of Graduation : April, 2006
University : Anna University, TamilNadu , India
College : Sri Ramakrishna Engineering College
Scores : Passed in First Class with distinction (76.2%)
PERSONAL DETAILS:
Date of Birth : 19/01/1985
Father’s Name : Kannappan
Marital Status : Married
Spouse Name : Balathandapani Palanisamy
Nationality : Indian
Passport Number : G6273730
Linguistic Skills : English, Tamil.
Hobbies : Reading Books, Listening to Music, Gardening etc.
I hereby declare that the information furnished above is true to the best of my knowledge and belief.
Place: Columbus
Date: (VIJAYALAKSHMI)
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