RESUME

MOIN BABA SHAIK : w032d0@r.postjobfree.com

: +91-903*******

Career Objective

To work where I am given the opportunity to passionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on the whole.

Education

M.Tech (VLSI System Design), JNTU University, Hyderabad, A.P

Sep 2011. GPA: 73.12%*.

B.Tech (Electronics and Communication Engineering), Kakatiya University, Warangal, A.P, May 2009. GPA: 63.12%.

Intermediate, Board of Intermediate, A.P, May 2005, GPA: 77.77%.

SSC, Board of Secondary Education, A.P, May 2003, GPA: 64.75%.

Summary of Skills

Proficient with coding RTL & Behavioral using Verilog.

Proficient with developing test environment for RTL verification, functional verification.

Proficient in developing appropriate test vectors using Verilog.

Proficient in writing fully automated test benches.

Experience with synthesis and optimization of Verilog code

Proficient in developing STA (static timing analysis).

Experience with FPGA implementation with Xilinx.

Worked on ISE simulator,

Experience with Physical design

Good communication skills

Achievements

Technical Paper publish in IEEE transaction in 2010

Design and Implementation of 16-Bit Vedic Multiplier.

Technical Paper publish in state level proceedings in 2011

Design and Hardware realization of a 16-Bit Arithmetic unit

Participated in ARM design tools National Level Seminar.

Participated in National level Seminar and received certificate on LOGIC DESIGN sponsored by XILINX.

Participated in CADENCE design work shop on LAYOUTS,RTL Simulator, and SOC Encounter

M.Tech Projects

1.16-BIT VEDIC MULTIPLIER

Implemented Design of 16-bit multiplier using Verilog HDL on Xilinx Spartan 3.

The design was simulated using ISE tool.

The design was synthesized using RTL compiler

The Timing constraints are met with SOC encounter

Role : Analysis & RTL Coding

Environment : Xilinx ISE tool

2.32-BIT ALU

Implemented ALU using Verilog HDL on Xilinx Spartan 3E.

The design was simulated Xilinx ISE tool.

The design was synthesized using RTL compiler

The Timing constraints are met with SOC encounter

Role : Analysis & RTL Coding

Software : Xilinx ISE tool

B.Tech Project

Title: DESIGN OF FREQUENCY MODULATOR (FM)

Project Synopsis:

This is a communication system one of development made to communicate mostly in military applications. It is an embedded project and has to Modulate and de modulates the audio input signal. This FM is also used as hamming radio during flood conditions. The project is intended to design a system that supports a wireless communication-using IR rays. The data (modulated signal) transmitted over the free space through antenna, is received by another device (Demodulator). So this is very useful to do operations like monitoring Temperature, and in military applications.

Role : Design engineer

Personal Profile

Name : MOIN BABA SHAIK

Father’s name : SHAIK ABDUL KHASIM

Address : H.No:3-2-198,

Chunchupalli village, Vidhyanagar colony,

Kothagudem post, Khammam district.

Date of birth : 28-08-1988.

Marital Status : Single.

Nationality : Indian.

Languages known : English, Hindi, Telugu & Urdu.

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