Ganga Ravi Kyatam

Surya Residency, Flat no ***, DOB: 14th December, 1981. Vysya Bank Colony, Email: vuzowu@r.postjobfree.com

Old Bowenpally, Secunderabad 500011, Phone No: +919*********.

Andhra Pradesh, INDIA.

CAREER OBJECTIVE

As a dedicated and highly motivated Electronics Engineer, I would like to add significant value to the organization by combining my theoretical knowledge and practical experience to deliver original concepts in the field of FPGA based systems or in the field of ASIC design and development.

EDUCATIONAL QUALIFICATIONS

P.G Diploma in VLSI Design from CDAC-ACTS, Bombay in Aug 2005

B.TECH. (ECE) with 69.05% from Shadan College of Engineering and Technology, Hyderabad(A.P) in April 2004

Intermediate with 84.4 % from Sri Vijaya Sai Junior College, Bodhan(A.P) in March 2000

S.S.C. with 72.16 % from Z.P High School, Pochampadu (A.P) in March 1998

SKILLSET (TECHNICAL, ORGANIZATIONAL)

Experience in Digital Logic Design and Static Timing Analysis

Expertise in FPGA design/RTL design flow with fluency in HDL coding.

Good control on VHDL/Verilog HDL in RTL synthesis point of view.

Good Experience in integration and implementation of RTL modules and on board testing.

Experience in EDA tools like Xilinx ISE, EDK, Accel DSP, System Generator and ModelSim.

Experience of using real time debugging tools like Xilinx Chip Scope Pro and Logic analyzer.

Good knowledge of Spartan-3, Spartan3E, VirtexII and Virtex-5 FPGA’s architecture.

Worked on Tri Mode Ethernet MAC Controller.

Worked on Virtex-5 IDELAY, IDDR and ODDR primitives.

Experience in FPGA based product design cycle.

Offsite working experience with Indian client.

TOTAL WORK EXPERIENCE (VLSI DESIGN ENGINEER) 5 YEARS

ORGANIZATIONAL EXPERIENCE

I) Designation : - Design Engineer

Organization : - CoreEL Technologies, Hyderabad

Duration : - November 2008 to till date (1+ years)

Company Profile : - The Company offers design services in the area of FPGA design, embedded design, PCB design and ASIC design with emphasis on quality deliverables.

2) Designation : - VLSI Engineer

Organization : - Wavelet Group, Pune

Duration : - 1st August 2005 to October 2008 (3 years 3 months)

Company Profile : - Wavelet Group is an authorized third party design centre for Xilinx inc. (USA) for VLSI based product design. It also works as a design house for image processing and digital signal processing (DSP) applications for commercial and defence organizations in India and abroad. Wavelet Group in brief, is an extraordinary combination of human expertise and consistent research methods to excel!

Projects: -

1) Developing AMBA AHB IP-IF (Complete Protocol Support)

This is completely developing AMBA AHB IP-IF module with complete protocol support. All peripheral are interfaced with IP-IF to communicate with AMBA AHB interface. In previous development all peripherals communicated with MPC107 memory interface module. This project includes complete verification of AMBA AHB IP-IF module.

HDL: Verilog (development), System Verilog (Verification)

Team Size: 1

FPGA device: xc5vlx110-1ff676

Location: RCI, Hyderabad

Tasks carried out:

Worked as a project engineer.

Understanding requirements, identifying basic blocks and preparing design document.

Design and Verilog Coding of AMBA AHB IP-IF module.

Developing individual test benches to test individual peripherals.

Developing BFM in System Verilog to test AMBA AHB IP-IF module.

Integration of all peripheral modules and tested.

2) Implementation of Tri Mode Ethernet MAC module with 256 point FFT module

This is completely FPGA based system with one MicroBlaze soft processor for 256 point FFT algorithm testing and host interface. The system is having 4 Virtex5 FPGAs, SPI memory, compact flash and one CPLD. Each FPGA interfaced with 6 FMC connectors to connect daughter cards.

HDL: VHDL

Team Size: 4

FPGA device: xc5vlx110-1ff676

Location: CoreEL Technologies Pvt Ltd, Bangalore

Tasks carried out:

Worked as a project engineer.

Understanding requirements, identifying basic blocks and preparing design document.

Design and VHDL Coding of Ethernet MAC controller interface with 256 point FFT module.

Implementation of Tri Mode Ethernet MAC controller using Virtex-5 IDELAY primitives.

Implementation of 256 point FFT module.

Generation and implementation of 1 MicroBlaze processor system with required p-cores.

C-coding of communication protocol for host interface.

Integration of all modules, implementation using XILINX ISE and EDK and on board testing.

3) Reliable High Speed Data Acquisition System

The system is designed for acquiring data from the four 8-channel Analog to Digital Converter (ADC) s (i.e. ADS1278). The acquired data is sent along with the Cyclic Redundancy Check (CRC) to ensure the data reliability. Data is then sent to the central controller unit using Aurora, a Link Layer Protocol, with which one can achieve gigahertz data-transfer rates in serial links without having to make trade-offs in data integrity. All control actions of the ADC will be performed using the ADC controller. ADC controllers Configuration and the entire system monitoring are done by the on-chip embedded processor (PowerPC440). Advanced features like IDDR (Input Double Data Rate), ODDR (Output Double Data Rate) and IDELAY primitives of VIRTEX5 FPGA's are used for data transfer and alignment with internal FPGA's clock.

HDL: VHDL

Team Size: 4

FPGA device: xc5vfx130t-1ff1738

Location: CoreEL Technologies Pvt Ltd, Bangalore

Tasks carried out:

Understanding requirements, identifying basic blocks and preparing design document.

Implementation of ADC data reading using Virtex-5 IDDR and IDELAY primitives.

Implementation of Aurora Link Layer Protocol using Virtex-5 FPGA.

Integration of all the modules with required clock generation logic and implementation using Xilinx ISE tool by giving required timing constraints.

Individual module and integrated testing on board.

4) Wireless Link over RF

The system is intended for use in wireless applications for RADAR parameter estimation and control. The system has two boards, first board consist of SPARTAN III E FPGA, Key pad (4X4), LCD and RF Trans receiver (CC2500). Second board consists of FPGA (Virtex II), TS-DSP @ 500 MHz and RF Trans Receiver. The system first handshakes to confirm the proper operation of both boards. On first board, FPGA acquires and update the RADAR data on RF link using SPI interface performs format conversion and displays the data on LCD (16 X 2) with strictly following timing and control signals. The FPGA (Vertex II) also updates / acquires the RADAR over RF link then data stores in to FIFO after successfully acquiring sends the data to TS-DSP for decoding purpose. After decoding FPGA updates / acquires the data on RF link

HDL: VHDL, Verilog

Team Size: 5

FPGA device: Spartan3E, VirtexII

Location: Wavelet Group, Pune

Tasks carried out:

Understanding requirements, identifying basic blocks and preparing design document.

Design and VHDL coding of controlling RF card.

Design of control system using PicoBlaze processor.

Integration of all the modules with required clock generation logic and implementation using Xilinx ISE tool by giving required timing constraints.

5) Data Acquisition and Analysis System

The system is designed for capturing data for Revolution per minute, Temperature, Acceleration and Noise of the vehicle under test. The system is having one master board and two slave boards. Master board consists of Spartan-IIIE (250K), CPLD (XC9572), BF-531 (@600MHz), RF Trans receiver (CC2500), two ADCs in which one ADC (AD7767) is acquiring Acceleration and Microphone data, Second ADuC (ADuC812) is acquiring Temperature data and RPM sensor. Slave board consists of Spartan-IIIE (250K), CPLD (XC9572), BF-531, RF Trans receiver (CC2500), and ADC, which acquires the data from microphone. The acquired data on Slave boards send to Master board over RF Link (500 KSPS data rate).This system is also interfaced with PC using USB-2.0 interface. The data is then used for analysis of optimum vehicle design.

HDL: VHDL

Team Size: 5

FPGA device: xc3s250E-4ft256

Location: Wavelet Group, Pune

Tasks carried out:

Understanding requirements, identifying basic blocks and preparing design document.

· Design and coding of ADC reading interface, RPM interface and RF controller interface.

· Individual module and integrated testing on board.

Offsite testing of the board with actual system.

6) Video Converter

The system consists of three Video decoders and Encoders. First decoder (AD9887) is having analog RGB interface and control signals; each 8-bit R-G-B output is fed to FPGA. Second DVI receiver (TFP401) is having digital visual interface, the output of this decoder is fed to FPGA for further processing. Third is LVDS receiver (THC63LVD104A) the output of this decoder is also given to FPGA. After the completion of processing (video format conversions) the output is converted to analog, DVI and LVDS using Analog RGB encoder (ADV7123), DVI Tx (TFP410) and LVDS Tx (THC63LVD103). FPGA also takes Parallel RGB input. FPGA plays the important role in programming video encoders and decoders using I2C and video data acquisition and conversion of the video data to user selectable video format. UART interfaced is provided for user selection facility.

HDL: VHDL

FPGA device: xc3s1000-4fg676

Location: Wavelet Group, Pune

Tasks carried out:

Coding of interface logic for on board peripherals.

Design and coding of I2C controller logic and interfaced with Video decoders and encoders on board.

Implementation of UART for Host interface.

Integration of all modules, Implementation on Xilinx ISE and on board testing.

REFERENCES: Furnished upon Request

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