HARIKA SURAM

**** *** ******** ****, #***** v94066@r.postjobfree.com

Philadelphia, PA -19130 267-***-****

_____________________________________________________________________________________________EDUCATION:

Temple University, Philadelphia, PA May 2011

Master of Science, Electrical Engineering, GPA:3.67/4.0

Kakatiya Institute of Technology & Science May 2009

Bachelor of Technology , Electronics & Communication Engineering, GPA:3.9/4.0

RELEVANT COURSES:

Digital System Design, Computer architecture, VLSI Physical Design, Microelectronics, Control System Analysis, Probability, Digital signal processing, Digital Image Processing, Communication Networks.

TECHNICAL SKILLS:

Programming Languages: C

Hardware/Assembly Languages : Verilog, VHDL, 8086

Tools: Matlab, Modelsim, Pspice, Xilinx, Quartus II 7.2, Multisim

Simulink, Latex

Operating Systems: Windows 9x/ME/2000/XP/Vista, Linux, Unix

Equipment: Oscilloscope, Signal generator, Voltmeter.

Others: HTML, MS Office, Adobe Photoshop

WORK EXPERIENCE:

Teaching Assistant - under the Prof. Dr.E L Turky, Temple University, PA Dec 2009-May 2010

Worked as Teaching Assistant for Dr E L Turky for the course of Electrical Devices and Circuits

• Responsibilities included Lecturing of Classes, Administration of under graduate students lab, Responsible for grading of papers

AV Support Technician, Fox School of Business,Temple University, PA Aug 2010- May 2011

• Responsible for managing all technology related service requests – Network Issues, Hardware and software problems arising from state of the art - 25 classrooms 20 breakout rooms and 8 computer labs.

ACADEMIC PROJECT EXPERIENCE:

Serial bit pattern detector Fall 2009

• Developed a serial bit pattern detector and keypad scanner using Verilog HDL synthesizable RTL.

The design is simulated in ModelSim and synthesis is done on DE2 board using Quartus II environment.

Design of a single Cycle Computer with MIPS-Instruction Set Architecture Spring 2011

• Verilog source code to implement a functional single cycle computer has been designed. The test benches have been written for various modules of the design

Advance Hardware Design Spring 2010

• Enabled a module which makes the FPGA communicate with a PC via Ethernet using UDP packets.

Division Hardware Design Spring 2010

• Verilog source code to implement the division hardware has been designed. Test benches have been written for various modules of the design and synthesis report was generated using Xilinx Spartan-3 XC3S200.

Hough Transform Algorithm Implementation Using FPGA Fall 2009

• Matlab and VHDL source code to Implement Hough Transform Algorithm has been designed and then implemented on FPGA

32 Bit Floating Point Adder Spring 2010

• 32 Bit Floating Point Adder has been designed using Verilog. Test benches have been written for various modules of the design and synthesis report was generated using Xilinx Spartan-3 XC3S200

ACHEIVEMENTS AND ACTIVITIES:

• Member of IETE (Institute of Electronics and Telecommunication Engineers)

• “Best paper award” Crawly Caterpillar Robot, Qubit-08 a technical symposium held at Mahatma Gandhi Institute Of Technology, Hyderabad, India

• “Best Organiser”, ELECTROCOM -06 a technical symposium at KITS, Warangal, India