SUMMARY OF QUALIFICATIONS:

Hardware Design, Systems Engineer and FPGA Firmware Engineer

Experience in all phases of product development from marketing research through design, testing, and sustaining

Extensive experience with multi processor/DSP embedded system design, real time algorithm development and parallel processing in FPGAs, high speed bus interconnects (e.g. PCIe and Ethernet), high reliability designs, complex system test and integration

Skilled leader, mentor and cross functional team development

Accomplished communicator with excellent presentation skills for sales, marketing and customer proposals

Ability to be flexible and multi task across several programs simultaneously

Ability to work in groups and brainstorm to find solutions to complex problems

Hardware: TI DSPs, PowerPCs, x86, Xilinx/Altera FPGAs/cPLDs, PCI & PCIe, 10/100/1G/10G Ethernet, ATCA, VPX, VME, Serial & Parallel RapidIO, DDR/DDR2/DDR3 SDRAM/QDR/FIFOs, DPRAMs, XAUI, WiFi, USB

Software: VHDL & Verilog, Synplify Pro Synthesis, ModelSim Simulation, Xilinx ISE/EDK/System Generator tools, Matlab, C/C++, Orcad, Allegro, DxDesigner, Viewlogic, Timing Designer, MS Office tools, Visio.

PATENTS:

Wireless Communications and Methods for Multiprocessor based MUD

Wireless Communications and Methods for DMA and Buffering of Digital Signals in MUD

PROFESSIONAL EXPERIENCE:

MIT Lincoln Labs (via DPC) Lexington, MA

Hardware Engineer – Active Optical Systems 2008-Present

Part of a small project based team of engineers that had to be flexible and capable of multi tasking between projects. Team members were organized by tasks rather than the traditional development roles which meant we had to be flexible, self motivated and self directed.

I was responsible for architecting, coding, integrating and testing FPGA code used in the processing of data received from various sensors and implementing algorithms used in the Military and SIGINT communities. Typically Xilinx Virtex 4, 5, or 6 FPGAs were used, but often times Virtex 2 Pro parts were selected for a rad-hard design, or Altera Stratix devices for sponsor specific programs. Designs were typically VHDL, but have also been mixed language designs with Verilog. Xilinx ISE and Altera Quartus software was used to build designs while simulation was done using ModelSim.

I was responsible for the architecting, designing, laying out and testing of prototype hardware boards/systems. Designs required the use of PCIe interfaces as well as 10/100/1000Mb Ethernet for moving data between elements in the system. Various serial buses were used for the command interfaces, such as SPI, I2C, or SFPDP. Systems were typically VPX, but depending on the application custom board formats and platforms were used. Designs consisted of multiple FPGA, DSP and embedded processors organized to enable parallel processing in the system.

The most demanding challenge to overcome here at the lab was that the implementations required a great deal of ingenuity and creativity to solve the problems of bandwidth and limited processing power to perform the functions in real time. It was required to be flexible, open minded and structured in the designs to accommodate the chance of changes or additions at any time.

Raytheon Tewksbury, MA

Senior Systems Engineer - Integrated Defense Systems Summer 2009

My role consisted of the architecting, procuring, integrating and testing of COTS components in a packet switched, secure IP based Communications platform for the Patriot Missile program. I was required to write the appropriate specifications, procedures and documents while working in a team to solve problems related to the integration and deployment of the systems communications infrastructure. I was the systems engineering interface to the electrical engineering and FPGA development groups on the project.

Microwave Radio Communications Billerica, MA

Principle Hardware Engineer – Research & Development 2007-2008

At MRC I was the lead digital hardware engineering for the R&D group. My role consisted of trying to update their antiquated approach with their analog designs to a more process oriented and structured approach, while incorporating and architecting digital components in their the new design. The most challenging part of working in this role was earning peoples “buy in” and understanding of the necessity of the new approach in order to keep the company competitive and allow for future growth in their market. The company had relied far too much and for far too long on past products and contracts that were becoming end of life and obsolete. This allowed me the opportunity to work side by side with Hardware, Software, Mechanical, Systems Engineering, Manufacturing, Marketing and Business Development to forge a plan going forward.

I was able to work directly with marketing to better understand the target market and help write a set of Marketing Requirements Documents for the new set of products. This required going to the customer’s site and performing interviews to understand their needs, required features and the human engineering aspects to the products. I worked directly with Systems Engineering so that I could understand and create the Systems Requirements Documents for the set of new products. I worked with manufacturing to understand the new work flow with the digital components. We worked together to form an automated set of test beds and procedures using JTAG, bed of nails testing and functional testing to maximize coverage.

My biggest task and achievement was working with the HW engineers and CAD people to educate them in digital design. I was able to mentor the young HW engineers in the use of hierarchal design methodologies, embedded processor designing, high speed memory, 10/100/1G Ethernet as well as other digital interfaces such as USB, I2C and front panel Touch screen interfaces. With the CAD folks we created a parts database that could be shared amongst all the engineers rather than everyone always creating their own symbols from one design to another. This allowed easier portability and leveraging of schematics from one design to the next. We changed the CAD tool from PADS to Allegro and created a footprint database so that we could leverage designs more affectively and improve design times when farming out designs to third party layout shops. I supported the CAD team in understanding the new and more complicated board materials and board stack-ups that were being required.

We formed a cross functional team and introduced a program manager role on the projects, working to create and maintain a schedule as well as identify problems and potential solutions.

The resulting systems we came up were either portable or rack mounted, which drove the form factor and size of the system. 1U, 2U or 3U sized systems were typical for the receiver, transmitter or IP networking products. The designs used Ethernet to pass command and control throughout the system remotely or a custom touch screen LCD front panel for direct access. Analog or digital video (Composite SD/HD, SDI–SMPTE259, HDSDI-SMPTE292M) and digital or analog audio signals (AES/EBU) were received/transmitted and mpeg decoded/encoded before being modulated using either COFDM(DVB-T) or SCM (QPSK to 64QAM) to a 70Mhz IF signal. Typical RF frequencies broadcast were 2-13 GHz.

Mercury Computer Systems Chelmsford, MA

Principle Hardware Engineer – Defense Alliance & Wireless Communications 2000-2007

I held the title of HW Design Engineer for several groups within Mercury; the Wireless Communications Group and the Defense Alliance Group. My responsibilities included designing multiple PowerPC, FPGA, and Ethernet based embedded systems as well as coding FPGAs for the Military, Medical and SIGINT communities. My design work entailed system architecting, documentation and test plan writing, schematic capture, timing analysis and simulation, board placement studies, board constraint definition, and board bring-up, debug and validation, HDL coding with various timing and placement studies in a variety of FPGA devices.

Some of the challenges I faced while writing FPGA code was interfacing high speed Race++ endpoints to different high speed applications. This provided me with an opportunity to write HDL code in high speed multi-time domain environments, requiring various timing constraints, placement constraining and hand placement. I was able to work with Xilinx to write a simple power routine that was scalable and could be added to existing code to represent potential applications or algorithms that have yet to be written. This was very useful in exercising up to almost 95% of the chip allowing placement, thermal and power analysis to be performed on future products. I also was able to work early on doing some R&D work embedding a PPC and Ethernet tri-mode MAC softcore to a high speed serial fabric in a multi processor computing environment. Several of these ideas and projects were absorbed by other groups within Mercury to eventually become products.

Board Design was also a large part of my responsibilities at Mercury. Some of the platforms I was able to design boards for were Vita 41, VITA46/48, ATCA, cPCI, and custom systems. Many of the systems were convection cooled, but I was able to work on Vita 46/48 specification development working with different companies to do conduction cooled and liquid cooled boards/systems too. Many of the challenges in these systems were just raw density of the boards. We pushed the envelope as to what could reliably be manufactured and tested. Boards ran upwards of 32 layers, using blind and buried technology and various high speed board materials. Power densities were on the order of nearly 300W in a 6U card. System speeds were in the multi GHz range for processors and hundreds of Mhz for IO and memory speeds. Serial data was passed around over differential lines topping the scales at 3.125Gbps and up. Different protocols were used to pass data such as PCI-E, Serial and Parallel RapidIO, 10Gbit Ethernet. These projects and research experiences provided me with a great deal of experience dealing with customer requirements, system architecting, design issues related to high speed signaling, thermal issues, and placement issues.

M/A-Com Lowell, MA

Senior Hardware Engineer – Wireless Communications 1997-2000

As a Hardware Design Engineer in the Wireless Communications group my responsibilities lay on designing heavily DSP and FPGA based systems for both the commercial and government markets. Design included DSP design with TI DSP’s and AMD/Intel embedded processors, high speed memory bus implementation, PIC micro-controller design and coding, Digital to Analog Conversion logic, FPGA design using Verilog/VHDL, Battery pack and Power Supply Design. Core responsibilities were with the design, HDL coding, layout, routing and testing of boards. Held security clearances of varying levels, from Sensitive to Top Secret compartmentalized requiring a polygraph, for different agencies.

Digital Equipment Corporation Maynard, MA

Senior Hardware Engineer – Low End Alpha Servers 1995-1997

My duties consisted of designing (including schematic capture, layout, and routing), simulation, testing and debugging of server motherboards. These designs included Alpha based server motherboards implemented with high-speed memory bus interfaces, PIC processor design and FPGA design was also required. Also performed various graphics and multimedia tests on ALPHA based systems. Testing included both hardware and software debugging as well as benchmark testing in Unix, Windows, and VMS operating systems.

EDUCATION: University Of Massachusetts At Lowell

• Bachelor of Science in Electrical Engineering.

• Master’s in Business Administration

• Master’s in Electrical Engineering

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