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Engineer

Location:
United States
Posted:
March 24, 2010
Email:
qpzw4b@r.postjobfree.com
Contact Info:
**********@*****.***


Sameer Jain
Camarillo, CA
510-***-****
qpzw4b@r.postjobfree.com

PROFILE
• Demonstrated experience in various aspects of Electronic packaging – Manufacturing (GMP), NPI, Assembly Materials (Eutectic/Lead Free/ESD/Moisture Sensitive), Quality (SPC, Cp, Cpk) and Process Improvement (Kaizan/Kan Ban/JIT).
• Demonstrated understanding of JEDEC, RoHS, IPC-A-610D, DFM/T/A and ISO 9001 requirements.
• Strong technical Project Management (PMP certified) and analytical skills with a focus on delivery results.
• Highly motivated team player with excellent communication and technical presentation skills.
• Effective multi-task with proven contribution in fast-paced environment.
TECHNICAL SKILLS
Process Equipment: OMNIFLOW 7 Forced Convection Reflow Oven, Heller Reflow Oven, MPM/ SPM/ Ultraflex Stencil Printer, Juki Pick and Place, Onyx BGA Rewok Station.
Test Equipment: Differential Scanning Calorimeter (DSC), Teradyne X-Ray Inspection System, Thermo Gravimetric Analyzer (TGA), Lansmont Drop Shock test system, Dage Series 4000 Ball Pull & Shear tester
Computer Proficiency: HLC Pick and Place programming, AOI Programming, Windchill PLM, Agile CM, GC Preview, AutoCAD, Minitab, JDE, Baan IV, Arena Simulation, EM Test Expert.
PROFESSIONAL EXPERIENCE
OSI ELECTRONICS, Camarillo, CA April’09 – Present
Process Engineer
• Managed production and manufacturing in maintaining SMT/PTH routings (screen printing, reflow, wave, 5Dx, AOI, ICT, Flying probe), creating drawing packages and interpreting instructions/ schematics for production floor.
• Designed and implemented new pick and place programs to increase placement of legacy components by 36% under cost reduction initiatives.
• Led various Lean Manufacturing and six sigma initiatives.
- Led Zero Defect initiative to reduce defects (BGA voiding, tomb stoning, solder bridging).
- Analyzed major CTQs using DFMEA technique.
• Conducted root cause analysis on soldering defects to recommend CAPA; led team of four engineers to improve yield to 98.2%.
• Lead team of engineers for verification and validation new SMT line equipments using IQ/OQ/PQ processes.
• Employed DFM/PDCA and FMEA methodology to improve yield and reduce failure rate.
• Travelled to Asian CM locations (Hong Kong, Singapore) for transition of prototype module into production and train production floor technicians.

ASYST TECHNOLOGIES, Fremont, CA Dec’07 – March’09
Manufacturing Engineer
• Implemented BOM automation system for wafer handling equipment product lines (and PCBA sub modules) to reduce structuring time from 2 hrs to 30 minutes.
• Designed and developed manufacturing processes to release MPIs and ECNs for new module introduction and changes for existing modules.
• Managed internal phase gate processes and design reviews, including requirements with production module planning and build with emphasis on system level tests.
• Implemented various efforts to improve material flow (U-shaped assembly cell), standardizing work flow, optimization supply chain process (value stream mapping).

SOLECTRON CORPORATION, Milpitas, CA Oct’06 – Nov’07
Project Engineer
• Led teams through various stages of new product introduction to ensure on time shipments of various electronic systems.

Sameer Jain 510-***-**** qpzw4b@r.postjobfree.com Page 2

PROFESSIONAL EXPERIENCE (continued)

- Designed and developed efficient manufacturing processes (PCBA assembly and system builds) along with maintaining MSDS for all acquired chemicals.
- Conducted Total Production cost (labor, material, fixed) assessment to determine product pricing.

• Attended customer meetings in support of business development and assisted in development of RFQ responses regarding new technologies and equipments.
• Defined process for monitoring lead levels in wave soldering; used SPC to regulate lead levels < 0.1% and demonstrated understanding of various electronics assembly materials like fluxes, encapsulates and conformal coating.

ALPHA METALS, Jersey City, NJ May’05 – Sept’06
Process Engineer
• Participated in product design, development and process validation of thermal protection device (CoolCapTM) for high temperature protection of heat sensitive components.
• Conceived, developed and implement manufacturing processes for PCB assembly and equipment for SMT and Thru-hole technologies involving stencil printer, pick and place and reflow ovens.
• Developed and executed designed experiments (DOE), problem solving, and decision-making tools in evaluation, selection, and implementation of process chemistries such as fluxes, coatings, adhesives and solders.

SKPM INDUSTRIES, New Delhi, India June’03 – Dec’04
Project Engineer
• Collaborated with engineering team in transferring paper manufacturing plant from Syracuse, NY to Jaipur, India.
• Analyzed equipment specification to support decision on initial design direction.
• Involved with different business development activities for specialty coated paper.
• Collaborated with vendors to develop process for quality and lead time consistency.
PUBLICATION
• Jain, S., Santos, D., Lewis, B., “Research and application of a thermal management device (CoolCapTM) for electronic assemblies”, Pan Pacific Microelectronics Symposium, Maui, Hawaii, January 2007.
AFFILIATIONS
• American Society for Quality (ASQ)
• Institute of Industrial Engineers (IIE)
• Surface Mount Technology Association (SMTA)
EDUCATION
• PMP, Project Management Professional, Project Management Institute (PMI)
• M.S, Industrial and Systems Engineering, State University of New York, Binghamton, NY.
• MBA, Preston university, WY
• Bachelor of Engineering in Mechanical Engineering, Bombay University, India