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C,C++,Matlab,VHDL,JAVA

Location:
chicago, IL, 60616
Salary:
25$/hr
Posted:
May 20, 2010

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Resume:

SAGAR BHOWMIK

**** * ******** ****** *******, IL 60616 qpg3ap@r.postjobfree.com 515-***-****

OBJECTIVE

Internship/Co-op in the field of Electrical Engineering in field of Digital Signal Processing and work with a team of highly experienced professionals.

EDUCATION

Master of Science, Electrical Engineering Expected: May 2011

Illinois Institute of Technology, Chicago IL GPA: 3.5/4.0

Bachelor of Engineering, Electronics and Communication July 2007

Visveswaraiah Technological University, India

SKILLS

Programming: C, C++, SystemC, MATLAB, VHDL, Verilog, PERL, Java, JSP, HTML, PL/SQL

Tools: Visual C++, Xilinx ISE, ModelSim, Cadence, Sue, Magic, ORCAD, Eclipse, Oracle

PROJECTS

Spectral Analysis and Audio Filtering using TMS 6713 C++

Implemented a real-time Audio Filtering using TI TMS32C6713 software development kit (SDK). The project used AIC23 Audio Codec to filter the audio stream using ping pong buffer implementation.

32-bit pipelined MIPS processor C++

Designed and simulated a 32-bit pipelined MIPS processor implementing five-stage pipelining taking possible data and branch hazards into consideration.

Network-on-Chip (NoC) Prototype SystemC

Extended a network consisting of two routers each connected to a processing element (PE). The PE communicates with both routers by sending/receiving packets to/from routers.

Audio Compression/Decompression MATLAB

Implemented sub-band coding scheme to achieve compression of audio signal. The tradeoff between quality and compression ratio was controllable.

Time Frequency Transformation Algorithms MATLAB

Designed Discrete Wavelet Transform, Short Time Fourier Transform and Wigner Distribution with MATLAB. The performance of each was compared using different types of signal.

DFT based on Goertzel, Cooley-Tukey & Rader Algorithms VHDL

Designed and implemented DFT using the three different methods. They were simulated and synthesized on FPGA to compare the resource usage and throughput.

Multiplier to Multiplier Accumulator (MAC) Verilog Modified the multiplier of ALU to MAC unit, enhancing the performance of CPU

EXPERIENCE - Software Engineer – Java, JSP, PL/SQL, HTML

Huawei Technologies India Pvt. Ltd., Bangalore India October 2007 – December 2008

• Developed and maintained several modules based on Web Technologies for the Huawei Internet Protocol Call Centre (IPCC) solution built upon the Computer Telephony Integration (CTI) platform. It was used as a Customer Relationship Management (CRM) application for call centre agents of China Telecom, MTN etc.

• Solely responsible for the module Bulletin and Memo System and added new features with zero defects.

• Nominated on performance basis to participate at Huawei Research and Development Center, China to learn the product development cycle and understand the complete functionality of IPCC solution.



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