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Design Engineering

Location:
New Delhi, Delhi, 110018, India
Salary:
3 Lakh
Posted:
April 24, 2012
Email:
qkauay@r.postjobfree.com
Contact Info:
******************@*****.***


OBJECTIVE:

Seeking a challenging position in VLSI industry where my engineering skills will greatly enhance the company's success and my personal growth.

QUALIFICATIONS:

****-** ** ** *******cal Engineering (GPA: 3.27/4) George Mason University, USA
2007-08 P. G. Diploma in Embedded Systems and VLSI Design CDAC, Noida, India
2003-07 B.Tech in Electronics and Communication Engineering (73%) PTU, India

SKILLS:

• Verilog, Design/Verification, VHDL, FPGA/ASIC Design, CMOS layout Design
• Mentor Graphics ModelSim, Aldec Active-HDL, Xilinx ISE, Xilinx XST
• Synopsys-Design Compiler/Primetime/Formality/Astro, Linux, Microwind 2.6
• C/C++, Linux, UNIX, TCL, Perl scripting, Microsoft Office Applications
• Communication Protocols: PCI, I2C, AMBA, RS232, USB, DigRF

WORK EXPERIENCE:

Jan’12-Apr’12 Design and Verification Trainee Masamb, Noida,India
Currently working with Masamb’s RTL Design Team to understand and develop a robust RTL architecture for DigRF v4 specifications by MIPI Alliance using Verilog. DigRF v4 will support upcoming broadband technologies such as LTE, Mobile WiMax.

Aug’09-Jan’11 Cryptographic algorithm RTL Designer GMU, Virginia, USA
The Luffa algorithm is one of the top candidates competing to become the next SHA standard. The project scope was to design the RTL of Luffa cryptographic algorithm with multiple architectures optimized for minimum Latency – area product.
• Realized 256 bit architectures of Luffa Algorithm (folded and unrolled)
• Designed optimized for minimum Latency - Area product
• Maximum use of embedded FPGA resources Xilinx (Spartan, Virtex) FPGAs
• The Datapath - Controller design done using ASM modeling with VHDL coding
• Designs verified(Block , Unit level) with test vectors

Aug’07-Feb’08 Embedded Systems and VLSI Design Trainee CDAC, India
• Modeled PCI bus Arbiter using Verilog coding.
• The design was synthesized for Xilinx FPGAs.
• Synthesis tools used: Xilinx XST and Synplify.

ACADEMIC PROJECTS:
Design of MIPS Microarchitecture using Verilog: George Mason University (GMU) Mini-MIPS is a 32-bit RISC architecture with a simpler instruction set to support R-type, Memory, and branch operations. Single-cycle, multi-cycle and 5- stage pipelined Datapath architectures implemented using Verilog. Each module is separately tested
Roles and responsibilities:
• Single-cycle and Multi-cycle Microarchitecture design
• 5-stage pipelined implementation of mini-MIPS architecture.
• Datapath and Controller design using Verilog HDL
• Test Bench Design for Functional Verification

Modeling of Sequential Multiplier: GMU, Virginia, USA
Implemented k-bit signed Radix-4 Sequential Multiplier with Radix-4 Booth Recoding based on the Shift/Add Algorithm, Right-Shift Version with Carry Save Adder optimized for the minimum product of latency times area.
Roles and responsibilities:
• Designed RTL Architecture of Sequential Multiplier in VHDL
• Radix-4 Booth Recoding used to realize a faster design
• Designed to achieve minimum Latency-Area product
• Parameterized Architecture and Test bench Design

RTL Design of Tree Multiplier: GMU, Virginia, USA
Implemented k-bit signed tree multiplier based on 4-to-2 reduction modules optimized for the minimum product of latency times area. The design is further optimized for the case of squaring. Pipelining introduces to add the capability of processing multiple sets of operands at the same time to achieve maximum throughput to area ratio.
Roles and responsibilities:
• Designed Array Multiplier architecture using VHDL
• Modeled to achieve minimum Latency-Area product
• Generalized RTL and Test bench design
• Functional simulation for Design Verification using test vectors
• FPGA synthesis and Implementation

ASIC Level Synthesis of SHA-1 Design: GMU, Virginia, USA
SHA-1 HDL Design was taken through all the steps of ASIC design flow such as synthesis, STA, formal verification, floor planning, placement & routing using Synopsys ASIC design tools.
Roles and responsibilities:
• Static Timing Analysis of SHA – 1 design performed using Design Compiler
• Design Verified using Formal Verification with help of Formality tool
• Floor Planning, Placement and Routing performed using Astro Synopsys tool
• 90 nm technology libraries used for design primitives
• TCL scripts used to automate the Synopsys tools.

Design of PCI bus Arbiter: CDAC, Noida, India
The PCI Bus Arbiter design is used for arbitrating multiple processors, some of which can be configured as the masters and others as targets. This is done with help of PCI arbiter ASM chart.
Roles and responsibilities:
• Modeled PCI bus Arbiter using ASM design in Verilog
• Verilog coding to realize the design
• Functional testing using Test Bench
• The design was synthesized for Xilinx Virtex FPGA.

Clock Driver Layout Design:
Clock distribution network layout designed using Microwind layout tool to get minimum clock skew and energy dissipation.
Roles and responsibilities:
• Designed a Balanced Clock driving network by doing buffer insertion.
• Designed to achieve minimum skew and energy dissipation and small area
• Implemented in a 0.25 μm CMOS process with 4 metal layers

High Gain CMOS Operational Amplifier (OpAmp) Design:
Schematic design of two stage OpAmp for the given specifications to achieve high output gain using current mirror in Orcad Pspice.
Roles and responsibilities:
• Schematic Design of the calculated OpAmp model
• Two stage Operational Amplifier model used to achieve high gain
• Modeling and simulations done using Orcad Pspice
PERSONAL INFORMATION:
Date of Birth: 19th Dec 1985
Hobbies and Interests: Chess, Sketching
Languages: English, Hindi, Punjabi

I hereby declare, that the above specified information is true to best of my knowledge.
MANINDER PAL SINGH