Process Engineer
Resume:
SPENCER PEARSON, JR.
Beaverton, OR 97007
E-mail: pota4m@r.postjobfree.com
OBJECTIVE
Process engineering position where my skills in process improvement can accelerate profitability.
SUMMARY OF QUALIFICATIONS
• Over 10 years experience as a process engineer in photolithography
• Skilled engineer with excellent process troubleshooting skills
• Extensive knowledge in the use of SPC and DOE in process control
PROFESSIONAL EXPERIENCE
Intel Corporation, Hillsboro, OR 2004 to 2010.
D1D Ramp Process Track Engineer – 300mm, 248 nm processes.
• Troubleshot process and equipment problems on TEL Lithius tracks.
o Maintained equipment at over 95% up to production rate
• Developed and executed game plans to recover from these problems.
• Monitored process parameters to verify health of equipment.
• Requalified equipment during process changeover.
D1C Process Track Engineer -300mm, 193 nm processes.
• Troubleshot process and equipment problems on TEL ACT12 tracks.
• Developed and executed game plans to recover from these problems.
• Monitored process parameters to verify health of equipment.
• Served as Litho representative to an IMT team charged with maintaining quality in the Fab for a process section.
o D1C Fab won TMG Excellence award for reducing inline defects by 50%
FSI International, Inc. Allen, Texas 2002 to 2003. Applications Laboratory Engineer. Supported field applications engineers by developing processes and solving process problems on the Polaris 2500/3500 Microlithography Cluster. Taught Polaris 3500 process applications class.
• Improved coat uniformity at a customer’s site by 20% using DOE and other methods.
• Developed a predictive mathematical coat thickness model based on process parameters.
International Sematech, Inc. Austin, Texas 2000 to 2002. Process engineer in photolithography on 193 nm program. Research projects included:
• Benchmarking of 193 nm photoresists
o Co-author “Current Performance of 193 nm Resists. Are They Ready for Production?”, Proceedings of the Microlithography Symposium Interface 2001, 2001
o Co-author “Patterning with 193 nm Resists”, 200th Electrochemical Society Meeting, September 2001. Paper published in the ECS Proceedings, January 2002.
o Co-author “Benchmarking 193 nm Resist Etch Resistance”, 10th International Symposium on Semiconductor Manufacturing October 2001. Paper published in 2001 IEEE International Symposium on Semiconductor Manufacturing, 2001
• Studying the effect of unfiltered light on 193 and 248 nm photoresists
o Principal author “The Effect of White Light on 193 nm and 248 nm Photoresists”, Proceedings of the Microlithography Symposium Interface 2001, 2001.
• Tool owner for DNS SK-2000 attached to a SVGL (ASML) Micrascan 193 scanner
Rmax, Inc, Dallas, Texas 1998 to 2000. Maintained and troubleshot processes in chemical mixing area for polyisocyanurate foam insulation process. Managed QA lab with supervision of a staff of three.
Hitachi Semiconductor (America), Inc., Irving Texas 1996 to 1998. Process engineer in Photolithography. Supported manufacturing in other areas including etch, LPCVD/CVD, and implant.
• Tool owner TEL M3000, Mark V, and Mark VII coaters and developers
• Tool owner OSI Metra 2150 overlay registration tool.
EDUCATION AND TRAINING
• University of Texas at Austin, BS in Chemical Engineering
• University of Mary Hardin-Baylor, Belton, Texas, MBA
• Design of Experiment training, taught by USAF Academy personnel at McLennan Community College, Waco, Texas
• Semiconductor Manufacturing Technology classes, TSTC, Waco, Texas
• TEL ACT 12 training courses
• TEL Lithius training courses
• Kepner-Tregoe training
Contact this candidate