Eduard Somin

Home: 905-***-****

Cell: 647-***-****

E-mail: l7zv1n@r.postjobfree.com

EMBEDDED SOFTWARE / FIRMWARE ENGINEER

(ADSP-21XX, PowerPC-74XX, Marvell GT64260 Memory/PCI Controller,

ATI GPU, MPC8308, QorIQ P1020RDB-PC)

OBJECTIVE

To work as software developer in an environment where my skills and

experience would help promote the goals and success of the organization.

TECHNICAL SKILLS

. Operating systems - vxWorks, Linux, proprietary RTOS.

. SDK - Linux Target Image Builder and Mentor Embedded Linux Essentials.

. CPU platforms - Freescale PowerPC, Analog Devices, X86.

. Graphics processors - ATI Technologies Radeon GPU Family.

. Programming languages - C/C++, assembler(PowerPC, Analog Devices),

VB6.

. Debugging techniques - using of Logic Analyzers, Bus Viewers and JTAG

Emulators in cooperation with board architects and FPGA designers.

. Configuration management - SVN, Rational ClearCase and ClearQuest.

. Standards - MIL-STD-498, MIL-STD-2167A, MIL-STD-2168, DO-178B.

. Documentation - ICD, SRS, SRDD, SWDD, STPD.

WORK EXPERIENCE

Richland Technologies LLC, Lawrenceville June

2011 - August 2012

http://www.richlandtechnologies.com

Position: Senior Software Engineer.

. Was responsible for research and analysis of the COTS boards for the

cockpit display project.

. Was responsible for bring up the Freescale Reference Design Boards

MPC8308 by using open source U-BOOT(universal bootloader) and Linux

version 2.6.29.6-rt23 (gcc version 4.1.2). Boot the board from NAND

and NOR memories. Implemented updating the kernel and rebuilt it by

using the LTIB.

. Deals with bring up the QorIQ P1020RDB-PC and QorIQ P1022DS.

Recompiled the Linux Kernel Version: 2.6.35 by using Mentor Embedded

Linux Essentials SDK for QorIQ Processors.

. Used USB TAP FLASH writer to restore U-BOOT in NOR and NAND memories

and wake up the system again.

. Ported the graphic application to the Embedded Linux Environment.

Tools and Environment: C, Linux, LTIB and Mentor Embedded Linux Essentials,

OpenGL ES.

Advanced Micro Devices Inc., Markham

June 2010 - June 2011

http://www.amd.com/us/pages/amdhomepage.aspx

Position: Senior Firmware Engineer, member of the GPU diagnostic group.

. Developed C++ test applications for clock generation PLL blocks for

different ASICs.

. Implemented the Factory Method Design Pattern to create the object

according to the ASIC ID, hide the differences between ASICs in the

diagnostic library and supply to the application the same interface to

the diagnostic capabilities.

. Designed and developed the diagnostic software library for Secured

Processor Unit (SPU) for encryption and decryption of the graphical

images. Implemented the API to the Firmware, that was responsible for

Encryption/decryption algorithms, ring buffer command/data interface

to this firmware and implemented numerous diagnostic scenarios.

. Used a Container Pattern to represent the group of the diagnostic

library objects as a single entity and to simplify using of this

library by the application suite.

. Created STPD document for using of SPU library for diagnostic goals.

Tools and Environment: C++, Linux.

ELTA Technologies Inc., Israel

May 1998 - February 2010

www.iai.co.il/17887-en/Groups_ELTA.aspx.

Position: Senior Software Engineer, member of the special purpose processor

group.

Duties: design, planning, implementation (C/C++ and assembly coding),

integration, testing, maintenance, documentation and customer support.

. 2008-2010: Diagnostic software CSCI running VxWorks 5.X on 5100/5500 SBC.

The application was responsible for loading and running embedded tests on

the MPC7410-based PPM-s (parallel processor modules) and test result

evaluation. The tests and their parameters were burned into the FLASH.

. 2007-2008: VB6 application for test and calibration of RF hardware

modules. GUI was based on the ActiveX controls for visualization of

different switch boards and it was oriented on the automatic test of the

settings for the sets of the RF frequencies.

. 2007-2008: Diagnostic software application for IO and three parallel

processor modules (PPM). The main goals were testing under the full load

(maximum data throughput and simulation of data processing overhead) the

data integrity, the right routing, getting test parameters and scenarios

from HOST/MC and supplying for HOST/MC criterions for evaluation of test

results.

. 2005-2007: Data distribution embedded CSCI (up to 40[MByte/sec]) for WBP

(Wide Band Processor), based on MPC7410 processors with AltiVec

technology implementation, assembled into the parallel processor modules

(PPM) on PCI platform and HOST test application CSCI (C

* Main capabilities of the embedded application:

V Initialization of Hardware (IO Interface - FPGA).

V Receiving data from the FPGA via PCI bus up to 20[MByte/sec] per

channel.

V Error detection in terms of hardware errors, framing errors and data

integrity errors (header only), error handling and recovery, error

reporting to PPMs and HOST.

V Build-in self test - data injection from FPGA to receiver DSPs via

Internal/External loopback, simulation and injection of errors into

receiver DSPs.

V Enable getting parameters from HOST/MC.

* Main capabilities of the HOST test application:

V Graphical User Interface (GUI) for definition, creation and

modification, loading and execution of the various test scenarios and

visualization of test results.

V The implementation of the HOST/TARGET communication by use of domestic

RTL services.

. 2003-2007: The Signal Processor Input Output (SPIO) embedded CSCI for

SARP system, based on MPC7410 processors with AltiVec technology

implementation. Below is the list of the main capabilities of the

embedded applications:

V Initialization of Hardware (IO Interface, Device Interface - FPGA, GT-

64260).

V Receiving/transferring data from/to Glinks up to 80[MByte/sec] per

channel.

V Data distribution of the received data to Parallel Processor Modules

(PPM) via switch unit, receiving of the processed data and its

transfer via LVDS bus to PDLI (PMC Data Link Interface).

V Error detection in terms of hardware errors, framing errors and data

integrity errors, error handling and recovery, error reports.

V Self test - Data injection from "master" to "slave" memory via GLINK

external loopback,

V Enable getting parameters from HOST/MC.

V Temperature measurement from the sensors via I2C bus.

. 1999-2005: Data distribution embedded CSCIs (up to 80[MByte/sec]) for a

group of the IAI radar projects, based on SHARC (ADSP21060), assembled

into the parallel processor modules (PPM) on VME or PCI platform. Below

are the main capabilities of the embedded applications:

V Initialization of Hardware (IO Interface - Altera).

V Receiving data from Glinks up to 40[MByte/sec] per channel.

V Recording data from Glinks (IO_RCV DSPs - DSP5 - FPDP - Recorder).

V Data distribution up to 10 Parallel Processor Modules (PPM) via FWY,

according to distribution algorithm.

V Error detection in terms of hardware errors, framing errors and data

integrity errors (header only), error handling and recovery, error

reporting to PPMs.

V Self test - Data injection from DSP5 to receiver DSPs via

Internal/External loopback, simulation and injection of errors into

receiver DSPs.

V Enable getting parameters from HOST/MC.

. 1998-2000: Signal Processor and Controller (SPC) CSCI for ground movement

detection radar project. SPC is embedded applications for multi-processor

SHARC (ADSP21060) board. I continued maintenance of this project up to

January 2010. Below are the main CSCs, interfaces and capabilities of the

applications:

V Initialization and build-in self test (BIT) components, ALTERA/SHARC

interface, HOST/SHARC communication interface, raw data acquisition

and its distribution for signal processing, target recognition and

reports to HOST, error recovery and azimuth/elevation controller.

Tools and Environment: C/C++, assembly for ADSP21060 and MPC7410

processors, domestic RTOS(EDEN) and VxWorks 5.X.

EDUCATION

. 1997-1998: Diploma in embedded System Programming, Bar Ilan

University, Ramat Gan, Israel.

. 1991-1996: BSc Degree in Mechanical Engineering at Israel Technion

University, Haifa, Israel.

. 1986-1990: Robots and Robotic Systems program at Byelorussian State

Polytechnic Academy, Minsk.

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