ASHWIN VASUDEVAN

*** **** **** ** *** ***,

Santa Clara, CA 95054

gxybtf@r.postjobfree.com

Ph: 573-***-****

Signal integrity engineer with four years of experience in designing high speed ASIC packages/PCBs and lab characterization seeking a position in a creative and productive environment with ample growth opportunities.

EXPERIENCE

CISCO SYSTEMS Inc. Santa Clara, CA

Hardware Engineer April 2007 – Present

Led the board, ASIC package design development and signal integrity analysis, from simulation to lab validation, working with different tools and interacting with vendors and cross-functional teams on a regular basis.

Extensively used Real time and Equivalent time Oscilloscopes, Network and Spectrum analyzers, and TDR and bit-error-rate test equipments.

TEXAS INSTRUMENTS Bengaluru, India

Intern, Signal Integrity and Timing (ASIC-SITI) group Aug 2006 – Dec 2006

Worked on Crosstalk glitch analysis and evaluating PrimeTime SI tool. Measured the Noise Propagated through different combinational cells characterized using Composite Current Source (CCS) modeling.

Wrote PERL scripts to automate the comparison between PrimeTime-SI vs. SPICE.

EDUCATION

Master of Science (Computer Engineering) December 2006

University of Missouri-Rolla GPA: 3.5/4.0

Bachelor of Engineering (Electronics & Communication) June 2004

Bharatiyar University, Coimbatore, India GPA: 8.3/10

SKILLS/TOOLS

Lab Equipment

R&S FSEM 26.5 GHz Spectrum Analyzer, Agilent N5230A VNA, Agilent DCAJ 86100C ET scope, Tektronix DSA 72004 20GHz RT scope, BERTScope S12500B 12.5 GHz Signal Analyzer & CRJ12500A Clock recovery unit, TEK P6245, P7380, P7313, P7320 active probes, GGB microprobes

EDA Tools

Sigrity PowerSI & Channel Designer, ADS, HFSS, Hyperlynx, SiSoft Quantum-SI & Quantum Channel Designer, HSPICE, Cadence Allegro, Polar Si8000 2D Field Solver, MATLAB, PERL

Operating Systems

Windows, Unix, Linux

PROJECTS

Serial Link Design

Analyzed and gave design guidelines for board to ensure minimal coupling and reflection for SerDes and Clock nets using HFSS and ADS.

Simulated serial link channels to determine mask violation at the receiver using ADS Channel Simulator.

Performed return loss and crosstalk simulations for SerDes nets on ASIC package in ADS using extracted s-parameters from HFSS 3-D model.

IBIS-AMI

Evaluated high speed SerDes AMI models from multiple semiconductor vendors on multiple EDA tools.

Provided feedback to tool vendors to implement and improve diagnostic features and chip vendors to ensure uniform AMI models across Cisco.

Created a specification document for Cisco’s requirement on IBIS-AMI models from chip vendors.

Power Integrity Analysis

Simulated & analyzed power plane impedance profile of ASIC packages and boards using PowerSI.

Ran transient simulations in HSPICE to meet noise spec at pin of ASICs.

Timing analysis

Defined interconnect topologies in the Pre-Layout phase, based on HSPICE simulations.

Diagnosed Post-Layout timing margins for different DDR interfaces using Quantum-SI tool.

Debugged timing failure on previously designed board and provided solution to overcome it.

Performed SSN and SSO analysis with extracted package nets in HSPICE for flip-chip & wire-bond ASICs.

Measurements & Lab Validation

Measured interconnects for SFP, CEI 6.25G, PCIE gen3 and XAUI interfaces using the Agilent N5230A Vector Network Analyzer (VNA) and high speed microwave probes.

Measured total noise at the pin of ASICs with traffic data running to determine violations for core and I/O power planes using real time Oscilloscope.

Measured the setup and hold timing margins for DDR and SDR interfaces with real time Oscilloscope.

Measured total jitter for interfaces including, PCIE, SFP+, XAUI using Real time Oscilloscopes and Sampling scopes and their respective built-in jitter decomposition software.

Worked extensively with different vendor based SerDes testability tools and features.

Performed SerDes parametric sweep for test chip, plotted behavioral trends for each parameter with channel lengths.

Tested the total jitter tolerance limit of high speed serdes receiver on vendor test chips. Measured total jitter generated by a high-speed serial link transmitter and compared the results shown by different instruments.

Calculated the phase noise of clocks using a spectrum analyzer.

Lab custodian; maintained records, documentation & calibration cycles of all instruments. Evaluated and recommended test equipment to the management.

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