Post Job Free

Resume

Sign in

Design Project

Location:
Bangalore, KA, 560049, India
Salary:
As per industry standards
Posted:
April 15, 2012

Contact this candidate

Resume:

CURRICULUM VITAE

SANTHOSH.C

M.Tech Degree in the field of VLSI Design and Embedded Systems.

Mail: ei6xx9@r.postjobfree.com Tel: +91-959*******

Objective

To serve the organization in which i am working by implementing the given task to the best of my ability and growing with organization.

Academic Record

M.Tech in “VLSI Design and Embedded Systems” in EPCET Bengaluru. Year of passing 2011.Percentage-78.38%.

B.E in ”Electronics and Communication” in GMIT Davanagere.Year of passing 2008. Percentage-65.34%

PUC in Nalanda Junior College Jagalur. Year of passing 2004.Percentage- 60.00%

SSLC in Government High School Jagalur. Year of passing 2002. Percentage- 70.88%.

Additional Training

Training on Low power VLSI design @ Indian Institute of Science, Bangalore for the period of 8 months.

Duration 8 months

Tools ICFB(CADENCE) , LT spice , Analog Artist with cds SPIICE, virtuso

Language VHDL

Description • Digital Design, Logic Synthesis, Low power techniques, DFT techniques, Static Timing Analysis.

• Floorplanning, Placement of macros and standard cells, Placement and optimization, Prototype global routing, Clock tree synthesis and optimization, Routing and Optimization techniques.

Technical skills

Operating Systems exposed: Windows XP, 7 and Basics of Linux

Programming Skills : Verilog, VHDL, C, C++.

Domain Skills : VLSI Design, Embedded System, ASIC Front End.

Assembly level languages : µp 8085, 8086 & µc 8051.

Tools : ICFB(Cadence), LT spice, Electric, cdsSPICE, virtuso.

Academic Project Details

1. Design and Analysis of Fast Low power SRAMs.

Conducted at: Indian Institute of Science, Bangalore.

Description: In this project I revealed a 1-kb 4-T CMOS SRAM by using the NWL(Negative Word Line) scheme to achieve low power dissipation. The proposed design does not need any special CMOS process, eg., multiple-well layers. The leakage current of the cell-access transistors is kept minimum as long as WL(Word-Line) voltage is below -0.4 V. Hence, the power consumption of the inactive cells in the standby mode is drastically reduced.

Contribution: 1. Made comparative study between 6T and 4T cells.

2. Study of Sense amplifiers and choose low power Sense amplifier for design.

3. Implementation of low power 1 kb SRAM.

Tools used: ICFB(Cadence), Analog Artist with cds SPICE, Virtuso

2. Multipurpose Surveillance Robot

Description: The aim of this project is to deal with controlling Robot wirelessly by receiving radio signals using DTMF technology through FM mode. Here we using PIC 16F873 microcontroller to achieve this objective. It uses a video camera for monitoring live events and has a few sensors. It can be extended to commercial standards.

Contribution: 1. Code development for stepper motor control.

2. PCB design for this project.

Components Used: Microcontroller (PIC 16F873), LED, Stepper Motor, Sensors.

Conferences

1) Presented a Paper titled “A 130nm SRAM with negative word-line and design techniques for low-power operation” in National level conference “HUMANTRONICS 2K11”conducted at JNN college of Engineering and Technology, Chennai.

2) Presented a Paper titled “Design and Implementation of Low power SRAM in 130 nm Technology” in National level conference “NCIT 2011”conducted at KARPAGAM University, Coimbatore.

3) Presented a Paper titled “Design and Implementation of Low power SRAM in 130 nm Technology” in National level conference “NACES 2011”conducted at M.S RAMAIAH INSTITUTE OF TECHNOLOGY, Bangalore.

4) Presented a Paper titled “Design and Implementation of Prototypical 250-MHZ CMOS 4-T Low Power SRAM in 130nm Technology” in National level conference conducted at SJBIT, Bangalore.

Personal Details

Date of birth : JAN 8th 1987

Gender : Male

Nationality : Indian

Marital Status : Unmarried

Languages Known : English, Kannada, Hindi.

Permanent Address : S/O Chandrappa V.B

Opposite Raghavendra Hospital

Jagalur Taluk

Davanagere (D)

Jagalur-577528

I hereby declare that the above-mentioned information is correct up to my knowledge.

PLACE : BANGALORE

DATE : 14 APR 2012 [Santhosh C]



Contact this candidate