RAVI SHANKAR GADDAM

*** ******* **. *** # ***, AKRON, OHIO-44304/ 330-***-****/ e49j50@r.postjobfree.com

OBJECTIVE

To obtain a challenging full time position in the field of Analog and Mixed Signal IC Design.

EDUCATION

Master of Science, Electrical and Computer Engineering Available immediately

The University of Akron, Akron, Ohio GPA 3.6/4.0

Thesis: Dual Plate Sampling Switched Capacitor DAC for High Resolution Mobile Display Drivers

Bachelors of Science, Electronics and Communications Engineering May 2008

VNR Vignan Jyothi Institute of Engineering and Technology, India GPA 3.9/4.0

Senior Design: Image transmission over Zigbee Network. The project includes establishing communication between Xbee devices using wireless zigbee protocol and an effective program is developed using C language to provide error detection and correction of the Image due to transmission path losses.

TECHNICAL SKILLS:

IC design tools: Cadence (Virtuoso Schematic & Layout Editor, Spectre, DRC, LVS, Diva, Assura)

Programming/Scripting languages: VHDL, Verilog-A, C, Java, Assembly, Python

Simulation tools: Pspice,LabView, Quartus, ModelSim, Matlab (&Simulink), MathCad, MultiSim, OrCAD

Operating systems: Windows,Linux & MS-DOS

WORK EXPERIENCE

Working and contributed as a Research Assistant on all these below projects.

Dept of Electrical and Computer Engineering, The University of Akron,Ohio May 2010 – Present

• Dual Plate Sampling Switched Capacitor 10 bit DAC for High resolution Mobile Display Drivers: Proposed a Dual Plate Sampling Scheme SC DAC that occupies 1/64 size of the conventional SC DAC. The Transistor level design was done after verifying the functionality using Verilog-A models to meet the specifications and to achieve low power, high speed for the opamp and also for the reference buffer to obtain low INL and DNL. Also followed various efficient layout techniques to match and make sure all devices to limit the effect of the process variations.This design proves that the capacitive DAC can be implemented with half the number of binary weighted capacitors and can achieve high speed,low power and high resolution without additional complexity and increase in area, power compared to all other DACs.

• Parasitic Insensitive 10-bit Switched Capacitor DAC for Large Sized Flat Panel Displays: Analysed the 2-stage modified Switched Capacitor DAC to understand the behaviour, non-idealities due to the process variations and also the parasitics associated with the capacitors. Worked and analysed the effect of parasitic capacitance and proposed a solution to make it totally insensitive to parasitic capacitance. Finally, only the behavioural model of the DAC was realised using Verilog–A models to show that it is insensitive to any amount of parasitic capacitance associated with the capacitors.

• Offset reduced Voltage Reference using Dual Plate Sampling Scheme: Designed,simulated and laid out the voltage reference specifically aimed for the Dual Plate Sampling Switched capacitor DAC using Dual plate sampling and auto zeroing technique. In this scheme the available capacitors of the proposed DAC are reused to generate the reference voltage,without increasing complexity and area compared to the conventional voltage references used in DAC architectures.

• Two-Stage Single ended CMOS Opamp:Designed, simulated and laid out a two-stage Single ended CMOS Opamp. The first stage is designed with a normal single ended Nmos input pair differential amplifier and the second stage is designed using a common source amplifier, the effect of the second pole is compensated using Miller compensation scheme and a series resistor is used to compensate the effect of zero.

• Two-Stage Fully Differential CMOS opamp: Designed,Simulated and laid out a fully differential CMOS opamp to obtain fully differential operation with two-stages. Implemented a switched capacitor Common Mode Feedback Circuit to maintain the output common mode voltages by controlling the gate voltage of the current source.

• Folded Cascode opamp: Designed, laid out a single stage folded cascode opamp using pmos input differential pair, Wide swing current mirror and verified using simulation to achieve a gain of 70dB, Bandwidth of 50MHZ and slewrate of 25V/us with a settling time of 125ns for a 4.2pF load.

• Currently working on Capacitor Mismatch and Switch Channel Charge compensation schemes to make the SC DACs robust to mismatches due to the process variations and switch charge in Switched Capacitor circuits.Various layout techniques like Common centroid, Multifinger and addition of dummy devices are also followed in the proposed DAC to limit the mismatch to the minimum due to process variations.

IC Testing Setup: Involves hardware design and software support for generation and capture of signals

• Hardware Design: Designed and implemented a PCB, hardware for testing the DAC IC.

Digital Pattern Generation and Analog Signal Capture

DAC requires a specific digital pattern to measure its performance. Generated the required Digital pattern using National Instruments multifunction DAQ to meet the design requirements. The analog signal generated from the DAC is captured using the DAQ with the support of the Labview tool. Developed Specific code to capture the analog output of the DAC at the instance of clock triggering and simultaneously logged to a file for further analysis.

Teaching Assistant

Dept of Electrical and Computer Engineering, The University of Akron,Ohio August 2009- April 2010

• Tools for ECE Lab: Assisted students in designing half –wave recitifier, testing of temperature sensor IC, Voltage regulator IC and design of other basic electronic circuits.

• Digital Logic Design Lab: Assisted students in programing MAX700 family EPM7128S reprogrammble PLD boards using VHDL language for course projects.

RELATED COURSE WORK

Analog IC Design, Data Converters, VLSI Design, Digital Integrated Circuits, Digital Signal Processing, Analog and Digtal Communications

AWARDS & ACHIVEMENTS:

• Awarded best outgoing undergraduate student, VNR VJIET, India, 2008

• Awarded Gold Medal for three consecutive years in undergraduation, VNR VJIET, India, 2005-2008

• R.S.Gaddam,K.S.Lee,Y.M.Lee,“Parasitic Insensitive 10-bit Switched capacitor DAC for Large Sized Flat Panel Displays”, Crystal Valley Conference and Exhibition, Korea, October 2010

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