Steve Huang

**** ****** ******

Palo Alto, CA ***06

(H) 650-***-****

(cell) 650-***-****

e0deiv@r.postjobfree.com

OBJECTIVE

A challenging position in the field of Networking, Storage Hardware, ASIC/FPGA chip design and verification.

SUMMARY

More than 15 years of ASIC/FPGA design, development and verification. Experienced in Mainframe, Networking, PC Interface, Disk Controller and Graphic ASIC chip. 2 years of defined, evaluated and developed System-on-Chip's IPs.

EXPERIENCE

Senior ASIC Design Engineer, HP, 6/10- 6/11

--Design and development of Data Transfer List for Core Switch.

--Implemented using linked-list data structure. Wrote Verilog and SystemVerilog code, ran simulation and verified using OVM.

Senior Design Engineer, CPU Tech, 8/18/08- 4/16/09

--Design and development of M1553 interface Altera FPGA in Verilog, PCB and bring-up.

--Design and development of 28VIO interface Altera FPGA in Verilog, PCB and bring-up.

--Design and development of RS232 interface Altera FPGA in Verilog, PCB and bring-up.

Senior ASIC Design Engineer, LSI Logic, 8/05- 12/06

- Verilog RTL coding, simulation for SPI4R’s tx and 2xgen hardmacros in FPGA.

-- Verified and check timing for SPI4R delay cell.

-- Verified and modified DDRII and QDRII Hardmacs.

-- Installed and verified ARM926EJ-S macrocell using Perl,C/C++ language.

-- Created top level and integrated the whole SOC chip.

Senior Design Engineer, TESSERA TECHNOLOGIES,San Jose, CA, 9/02-4/05

-- Designed and developed high speed 2GHz ADC board for radar application.

-- Designed and developed 2GB registered DDR DIMM for Opteron server using 8 stacked DDR memory.

-- Defined and coordinated 20GB flash drive development from concept to finished product.

Staff Design Engineer, LUCENT TECHNOLOGIES,Sunnyvale, CA, 10/01 – 8/02

-- Designed and developed ATM using 2 million gates Xilinx FPGA (Virtex II) from Scratch to the system bring-up.

-- Assigned the pin list, synthesized the Verilog design using Leonardo synthesis tool, ran FPGA simulation, performed FPGA place and route, analyzed detailed timing, constrained I/O timing and configured the FPGA to the PCB.

-- Coordinated firmware, PCB, and FPGA and bring up and verified the system.

-- Used Vera to verify DSL Access Multiplexer FPGA (ATM, UTOPIA and STM).

-- Setup Vera testbenches for DSL access multiplexer ASIC.

-- Generated testcases for CPU interface, ingress data path, egress data path, multicast, vc merging and Verified the design.

Staff Design Engineer, MITSUBISHI CORPORATION, Sunnyvale, CA, 8/99- 8/01

-- Responsible for three ASIC chips from verification to generate test vectors for production.

-- Place and routed for modules using Deep Sub Micron design methodology.

Staff Design Engineer(Project Lead), HITACHI CORPORATION, San Jose, CA,12/95 - 7/99

-- Lead the design effort for the Application Specific Module included PCI, USB, Irda, CAN and Ethernet Controller modules. Setup the Verilog and Synopsys design environment. Simulate and synthesize the modules and released the completed modules to system department.

-- Modified and verified Graphic Engine block and AGP block for Graphic Chip.

-- Designed ATAPI Interface block that include Auto Transfer, Packet Command, Task File Register and Data Path for Host and Device transfer.

Senior ASIC Engineer, QUANTUM CORPORATION, Milpitas, CA, 1/93 - 11/95

-- Started from PCMCIA specification, defined overall architecture of chip requirement, designed PCMCIA Interface and modified existing ATA design for 1.8" disk drive, wrote test patterns and simulated the whole design.

-- Converted NEC Microprocessor Interface schematic to Verilog code, assessed all the design detail and wrote fully automated synthesis script file, wrote test patterns that covered every condition and simulated the design, completed the design without bug and released to major product for mass production. Also used by multiple chips program in company.

-- Verified Fast-ATA, Servo controller, CD-ROM Controller and NEC microprocessor interface using TI methodology. Completed the design and manufacturing for multiple drive products.

Senior System Design Engineer, AMDAHL, Sunnyvale, CA, 9/91-12/92

-- Defined and designed SCSI interface for IBM mainframe storage director.

-- Defined and designed overall aspect of IPI repeater specification.

Senior Design Engineer, HITACHI CORPORATION, San Jose, CA 9/89-8/91

-- Started from EISA slave chip specification and designed the whole chip from using Mentor Graphic design tools. Wrote detail test

-- Started from EISA master chip specification, designed FIFO and JTAG section of the chip using Verilog Hardware Description Language.

Design Engineer, UNISYS CORPORATION, Santa Clara, CA, 2/87 – 8/89

-- Designed and development IBM 3380 DASD ASIC chip using LSI Logic design methodology.

-- Generated schematic and ran logic simulation on Mentor Graphic platform.

-- Wrote AC test patterns for TSSI, sentry tester and GENRAD in-circuit tester.

Design Engineer, EVEREX CORPORATION, Fremont, CA, 1/85 – 1/87

-- Designed and development IBM PC motherboard and Intel 8085 emulator for tape controller.

-- Designed and developed 125w, 300w, 500w switching power supply.

R & D Engineer, QUINTAR CORPORATION, Taipei, Taiwan, 1/80 – 1/82

-- Designed and developed UART for remote control scanner system.

-- Designed and development universal timer for missile-use battery charger.

EDUCATION

MSEE, MANHATTAN COLLEGE, New York – 1984

BSEE, NATIONAL CHENG-KUNG UNIVERSITY, TAIWAN – 1980

DESIGN TOOLS

RTL (Verilog, VHDL), SystemVerilog, VMM, OVM, Synopsys, Primetime, Vera, JTAG,DFT, MEMBIST, Mentor Graphic (Modelsim), Leonardo, Altera FPGA, Xilinx FPGA, C/C++,

Cadence ConceptHDL, Allegro, Constraint Manager,Logic Analyzer.

REFERENCE

Available upon request.

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