OBJECTIVE: Highly meticulous, smart professional digital designer with hands on experience in planning, designing and verifying the complex digital ASICs. Looking for challenging digital design position to perform definition, architecture, circuit design and verification.

EDUCATION

Master of Science in Electrical and Computer Engineering (August 2005- August 2007)

Mississippi State University, Starkville, MS

Majors in Computer Architecture GPA: 4.0

Bachelor of Engineering in Electronics and Communication (July 2000-May 2004)

Thapar University

Class Rank: 2 / 66 CGPA: 9.63/10.0

TECHNICAL

CAD Tools: Modelsim, NCSim, Xilinx 11.1, Synopsis DC, Verdi

Assembly Language: Microprocessor 8085, 8086, TPF

Database: SQL Server 2000, SQL Server 2005

Data Structure: Linked List, Binary trees, Queue, Stack

Networking: Socket Programming, Knowledge of TCP/IP model

Languages: Ruby, System Verilog, Verilog, VHDL, C++, C#, TCL, Perl

Operating Systems: Linux, Unix, Windows

Others: Object Oriented Concepts, I2C Interface, Synthesis, FPGA Emulation, TDM,

I2S mode, UVM, ECO, DFT

RESEARCH

January 2006 – August 2007

Developed a new architecture for Network Interface Card for multiprocessors systems and priority applications. In proposed architecture, the Network Interface Card will have multi ports for packet buffer, so that multiple processing can be done. Also, developed an algorithm, History Based Dynamic algorithm (HBDA), and designed a simulation model using VHDL and simulated using Modelsim for Memory Management algorithms in Network Terminals, as a part of research. Experimental results show that HBDA improves the packet loss ratio by 11.0 % to 16.1% compared to conventional dynamic algorithms in Network Terminals.

PUBLICATIONS

Shalini Batra, Yul Chu and Yan Bai, “Packet Buffer Management for a High- Speed Network Interface Card,” in the proceedings of 16th IEEE International Conference on Computer Communications and Networks (ICCCN 2007), Honolulu, Hawaii, USA, August 13-16, 2007 (acceptance rate: 29%).

WORK EXPERIENCE

August 2008- Current Digital Design Engineer, Maxim Integrated Products, Austin, TX

AX54: I2S/PDM digital input class D: Designed and implemented digital signal processing firmware including Interpolation, FIR, IIR, DC Blocking filters for audio and voice mode for DAC Path. Wrote System Verilog Models for the filters to verify the firmware. Used Wishbone Bus Architecture and FIFO’s for interacting the DSP with other blocks. Implemented Digital Audio Interface for TDM and I2S Mode.

AX57: AUD3042 mono audio subsystem: Designed, implemented and verified digital Automatic Level Control (Noise Gate and DRC logic) IP using Verilog. The ALC is configurable for different attack time, release time and expansion and compression ratio. Designed and implemented and verified the I2C interface, volume slewing for the digital core of the chip. Also did mixed signal verification using AMS. Generated production test vectors. First time success in the Silcon.

VA85: Quad Video Codec with Frame Sync: Took the lead to design and implement Internal Common bus and mixers. Designed and implemented “Digital Audio Interface” for TDM Mode, I2S mode and Audio Mode. Implemented and verified A-law U-law Encoding algorithms using Verilog. Did system level verification of the digital core using NCSIM. First time success in the Silcon.

AX21: S18 Audio Subsystem with Mono Class D Speaker Amplifiers: Took the lead for designing and implementing the digital core of the project. Designed and implemented the digital core including I2C Interface, Volume Slewing, power limiter, DFT. Successfully completed the project in First Rev without any major bugs. Designed, verified, tested, synthesized and generated the test patterns for the digital core of the project.

AX14: High Performance Multimedia Codec for Handsets: Designed IP vault “Digital Audio Interface” for serializing and de-serializing data. The module supported Intel TDM Long and short Format, I2S Format and Audio Format. Designed and implemented bridge between two clock domains blocks. Took the initiative to do FPGA Emulation of the digital cores using Xilinx Virtex 5 FPGA.

January 2007- August 2008 Engineer, ePsolutions LLC, Austin, TX

Responsible for designing robust, scalable and reliable solutions, implementing maintainable software for the design, documents and reviews the solution using C#.NET and SQL Server 2005 at the back end.

September 2005- December 06 Programmer, Mississippi State University

Developed user-friendly screens using PHP, JavaScript and HTML for carrying out experiments.

June 2004- July 2005 Engineer, International Business Machines (IBM), India

Air Ticketing and Access Plus work for WORLDSPAN. Developed database management system in TPF-Assembly Language. Responsible for converting TPF Assembly modules to TPF–C Modules.

AWARDS CERTIFICATIONS AND PERSONAL SKILLS

• Completed three days Xilinx FPGA “Design for Performance” and “FPGA Essentials” Training

• Awarded Scholarship and Certificate of Merit and Scholarship by Director, Thapar Institute of

Engineering and Technology (TIET), every year throughout the B.E program.

• Passed National Level Science Talent Search Examination, a scientifically designed skill based assessment test organized by Unified Council, India. Was awarded National Scholarship for outstanding performance in the exam.

• Certificate of Merit awarded in Mathematices by All India Senior Secondary School Examination (AISSSE) in 1998.

• Involved in lot of leadership activities at Thapar University: “Hostel Proctor”, “Cyber Incharge”, “Wing Incharge”.

PROJECTS

16 Bit RISC Processor: Designed and developed the Data path, FSM for a 16 bit RISC Processor using C language.

Developed Simulation Model for Bellman Ford Routing Algorithm using C++.

Pong Game: Developed two player pong game using Spartan III and PS-2 keyboard.

Balloon Hunt: Developed balloon hunt game using Spartan III and PS-2 keyboard.

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