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Design Project

Location:
bangalore, KA, 560010, India
Salary:
3laks
Posted:
May 04, 2012

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Resume:

MADHU S

Address: #***/**,*** *****,********** building,

Maragondhanalli,hullimangla post,

Electronics city,

BANGLORE-560100

Contact: +91-889*******

E-mail: d1lnby@r.postjobfree.com

CAREER OBJECTIVE:

To pursue a meaningful and challenging career that enables me to acquire knowledge and work towards organizational and personal growth in the field of vlsi.

ACADEMIC QUALIFICATIONS:

QUALIFICATION COLLEGE/UNIVERSITY YEAR OF PASSING PERCENTAGE

X(CBSE) J S S Public School March – 2005. 70.8 %

PUC(PCME) Sarada Vilas PU College March – 2007. 75 %

B.E (Electronics and Communication) Visvesvaraya Technological University

July – 2011 62.80 %

TECHNICAL SKILLS:

• Attended a certification course in VLSI conducted by industry professionals organized by VVCE-IEEE branch which

Covered Digital frontend design, Analog Circuit Design, Analog Layout design & techniques, Standard Cell Design and

ASIC Physical Design using Cadence R EDA tools for duration of 6 months.

• Good knowledge and hands-on experience in the fields of VLSI frontend design (using synthesizable Verilog),testbenches and VLSI analog layouts.

• Good knowledge and hands on expierence in verification.

• EDA Tools: Cadence EDA Tools (Virtuoso Schematic Editor, Virtuoso Layout Editor, Analog Design Environment, Assura

and NCVerilog ), Xilinx ISE, ModelSIM

• HDLs: Verilog, VHDL

• Operating Systems: Linux, Windows

• Other languages: C, Matlab.

PROJECTS:

1. Final Year Project:

Title IMPLEMENTATION OF DIGITAL WATERMARKING TECHNIQUE FOR IMAGE SECURITY AND AUTHENICATION

Tools: : Matlab, Cadence NCVerilog, RTL compiler

Description: The project relates to get the dct value of an image in matlab and writing Verilog code for the Datapath for all the 2 basic block of a digital watermarking i.e., visible module and invisible module. The visible module consists of submodules which includes calculation of mean and variance of an image,detection of edge blocks,scaling and embedding factors and finally an insertion module to scale or embed an image.while invisible module consists of lfsr and insertion module.Both modules are combined to provide the digital right management to multimedia images.

2. Course Projects:

(i) Title: An 8- bit processor design in Verilog using Cadence tools

Tools: Cadence NCVerilog, RTL compiler

Technology: TSMC 180nm

Description: In this project we have designed a data path for all the three basics blocks of a processor i.e. Decoder, ALU and Memory. This processor performs the entire basic 8- bit operations such as the arithmetic and logical operations. All the basic instructions was coded in Verilog and simulated and synthesized. TSMC 180nm standard cell libraries are used for synthesis.

(ii)Traffic Light Controller:

In this project we have designed a datapath and control path for three basic blocks(i.e. counter,decoder,statemchine).Here counter counts for a specific duration of time and resets,while decoder decodes the signals and statemachine works has a control signal.

(iii)FIFO:It consists of two controls signal one write control and other for read control,these control signal consists of flags to indicate the fifo is full or empty and one memory block to write and read the data .

3. Standard Cell Design:

Part of a standard cell library was designed and layout was done utilizing minimum area. The cells included

NAND3 2, OAI 4, NORX2, INV 4, OR2 1, ADDHx2.

Tools: Cadence Virtuoso Schematic Editor L, Cadence Virtuoso Layout Editor XL, Cadence Analog Design

Environment, Cadence Assura DRC, LVS, RCX.

Technology: TSMC 180nm ,TSMC 45nm.

Co-curricular Activities:

• Attended 1 day workshop on Long term evolution-march towards 4G conducted by Department of E&C, VVIET in 2010.

PERSONAL DETAILS:

Date of Birth : 22nd May 1989

Languages spoken : English, Kannada, Hindi

Hobbies : Travelling, Listening to Music, pc and xbox games ,playing football

Current address : #175/10,2nd floor,chandrappa building,Maragondhanalli,hullimangla post,

Electronics city,BANGLORE-560100

Permanent Address: #251,8th cross, ’C’ Block,j.pnagar,mysore-570008.

PERSONALITY TRAITS:

• Positive Attitude with a Strong Determination to Achieve.

• Punctual, honest and flexible to work

• Commitment towards my work

• Ability to work under pressure

•Motivated self-starter with desire to learn



Contact this candidate