TAEHOON KIM

, Los Gatos, CA, *****

408-***-**** • cg2ksq@r.postjobfree.com

MAIN OBJECTIVE

I would like to be a principal logic/analog/RF/memory device engineer who can also lead a process integration.

PROFESSIONAL EXPERIENCE

ACTEL: February 2010- Present

Principal Device/Integration Engineer

I have been in charge of eNVM (Embedded Non Volatile Memory) as integration/device engineer. I also have an experience in developing DTP package/electrical specification. I also have an experience in developing a process integration of 65nm technology with UMC of Taiwan.

AMD/SPANSION • Sep 2001-Feb 2009

MTS Device/Integration Engineer

I have been working as a device/integration engineer of HV/MV/logic/memory transistor. I also have an experience of developing a process integration of 45/35nm NAND product with TSMC of Taiwan. I also have an experience in developing Front/Back-End test structures of 45/35nm technology from a concept to layout.

AREA OF INTERESTS

Process Integration/device of logic/analog/logic/flash/RF devices.

AREA OF EXPERTISE

-Device characterization/Process Integration of 65/45/35nm technology with a foundary such as TSMC and UMC of Taiwan.

-Knowledge and experience of developing for High Voltage/Medium Voltage/IO/logic/flash memory.

-Experience of developing a setup/programming of manual/automatic wafer testing.

-Knowledge of reliability assessment for High Voltage/Medium Voltage/IO/logic/flash memory.

-Developing DTP package/electrical/geometrical design rules for 65/45/35nm technology.

-Developing Front/Back-End test structures of 45/35nm technology.

-Knowledge/Experience about RF IC and system.

-Knowledge of HSPICE/CADENCE simulation.

EDUCATION AND CREDENTIALS

University of Texas at Austin • Aug 2001

PhD, Electrical Engineering/Semiconductor.

Course credits from Silicon Valley Technical Institute 2010:

RFIC Design. Analog Circuit Design

PROFESSIONAL EXPERIENCE

ACTEL February 2010-Present

Principal Device/Integration Engineer

I have been a principal integration/device engineer in development of a low power 65nm generation programmable analog/logic array product of ACTEL. The following is my responsibility.

- Developing DTP/electrical specification for embedded memory.

- Testing/analysis of test structures and arrays.

- Developing a process with UMC of Taiwan.

- Process integration of High voltage/Medium Voltage/IO/logic transistors.

- An experience in working with a design team.

AMD/SPANSION • Sep 2001-Feb 2009

MTS Device/Integration Engineer

I had been a device/integration engineer in development of 130/90/65nm NOR flash memory from 2001 to 2007. The following is my responsibility.

- Process integration of High Voltage/Medium Voltage/logic transistor and flash memory.

- Developing electrical specification and process conditions for High Voltage/Medium Voltage/logic transistor/ESD/BJT transistors.

- Testing/analysis of test structures and arrays for High Voltage/Medium Voltage/logic transistor and flash memory.

I have a knowledge/experience in a layout/process integration/testing/programming/analysis. I am familiar with all details about process flows of flash memory. This includes processes such as STI/liner/oxidation/…/Co-Si or Ni-Si process/Contact Etch/Terminal Metal.

I had been also an integration/device engineer in development of 45/35nm NAND flash memory from 2008 to 2009. The following is my responsibility. I have an experience in spike anneal and Ni-Silicide process.

-Developing Scribe line monitor test structures of Front-End to Back-End. It includes SONOS memory array/High Voltage/Medium Voltage/IO/logic transistor/BJT/Metal-to-metal bridging/Continuity structures. I also have an experience in designing test structures of Ring Oscillator and SRAM.

- Process integration of High Voltage/Medium Voltage/logic transistor and SONOS flash memory array.

- Developing/testing electrical specification and process conditions for High Voltage/Medium Voltage/logic transistor/ESD/BJT transistors.

I am familiar with manual bench and automatic testing of a wafer. I know very well many analytical/statistical programs to handle electrical test results of wafer. I am also familiar with creating proper electrical parameter sets for test structures. I also have an experience with the following structures.

-All reliability test structures such as electromigration, TDDB and more. Field Vt structures, Diodes, Capacitors, BJT, Metal/Poly continuity/bridging structures, continuity/bridging structures with ~40nm, Well to Well leakage and Latch-up structure and more.

The following is a summary.

- A device/integaration engineer of 130-65nm NOR and 43/35nm NAND.

- A good knowledge of Electrical/Geometrical Specifications.

- A good experience in debugging device/process related problems related to analog/logic/memory devices.

- An experience in process integration.

Professional Skill

I am very familiar with developing DTP package including Electrical Design Rules and Geometrical Design Rules for both analog (HV/MV) transistors, flash memory and embedded memory.

I am very familiar with manual/automatic testing of wafers.

For data analysis, I have been using many programs, such as RS/1, GENESIS, JMP , SPOTFIRE, Basic and MATLAB and more.

I also know HP Basics and a programming language of HP V5000. I also have an experience using common layout tools, such as IC and VIRTUOSO. I also know well about HSPICE/CADENCE circuit simulation.

The following is a summary.

- A bench testing and an analysis of test parameters on cell, wafer and sort level.

- An experience of developing a design package with Electrical Design Rules and Geometrical Design Rules.

- An excellent knowledge about a device physics and many measurement techniques (C-V, Quasi C-V, Charge pumping, --- ).

- A good working knowledge about analysis and layout tools.

- A good understanding of future technological trends of nano-scale transistors, such as 32nm High-K/Metal Gate transistors, FDSOI, FINFET (Double Gate and Tri Gate) and SOTB.

OTHER EXPERIENCES

ROCKWELL SEMICONDUCTOR• June 1996-Aug 1996

SUMMER INTERN

I had an experience in a process integration of high current gain BJT. Because BJT used N+ doped Poly Silicon as Emitter, it needed nitride spacer to secure enough space between Emitter (Poly Silicon) and a contact to Base. This BJT is intended for high speed application for communication.

GOLD STAR ELECTRIC (S. Korea) • Mar 1985-Aug 1990

Electrical Engineer

I have been involved in a design and testing of multiple-band RF (microwave) transmitters and its control system. The work included a design of a control circuit and communication protocols between many modules, software design and a testing of a full system. I learned a skill of a circuit testing and C language programming. The following is a summary.

- Testing and integration of microwave devices including amplifiers, antennas, coupler, filters and so on.

- I am familiar with network analyzer, oscilloscope and logic analyzer.

- Setup of command protocol and implementation of a decorder and signal generator.

- Experience of designing system operating software.

Professional Training: January 2010 - May 2010

SVTI (Silicon Valley Technical Institute)

RFIC design:

I am very familiar with R, L and C matching circuit design in front end of RF receiver including L-match, T-match and Pi-match. The following is my area. I also have 5 years of experience working in RF systems.

- Design of broad and narrow band RF amplifier such as cascade circuit, zeros, poles, neutralization and unilateralization of Miller capacitance.

- Experience in PSIPCE or Cosmos simulation of RF circuit.

- Quarter-wavelength impedance transformer/TL and

- RF mixer design such as single and double balanced mixer.

- Power amplifier, such as class A, B and C.

- Noise Figure and a design of low noise amplifier.

Analog Circuit Design:

I know all of the following. I also am familiar with HSPICE simulation of analog circuit.

- HSPICE modeling of MOSFET

- Design of Current Mirror such as Wilson, Wide swing cascode, Self-biased cascode and regulated cascade and more.

- Design of Band gap reference circuit for Temperature and Supply-Independence.

- Design of Operational Amplifier/Frequency compensation such as elimination of RHP zero.

EDUCATION AND CREDENTIALS

University of Texas at Austin • Aug 2001

PhD of Electrical Engineering/Semiconductor

Korea Institute of Science and Technology • Mar 1985

M. S. of Electrical Engineering/Microwave(RF) Engineering

Seoul National University • Feb 1983

B. S. of Electrical Engineering

ACADEMIC WORKS AND PUBLICATIONS

I have been involved in a building of a new Rapid Thermal Proccessing CVD chamber in University of Texas at Austin. The main purpose was a growth of various SiGe layers and SiGe dots. The application was to make a various FETs and memory cells with quantum dots and High-K dielectric. The structure was tested in bench for its electrical characteristics and a programming/erase behavior of memory cells. I also have an exprerience in using a device simulation program to extract model parameters of mobility for SiGeC. The follwing is a list of publications done in University.

1. PhD Dissertation: Silicon Germanium Modulation Doped FET by Rapid Thermal CVD.

2. Taehoon Kim, Xiao Chen, S. K. Banerjee, “Growth of Relaxed Silicon Germanium Structure by RTPCVD,” TSF conference 1999.

3. Taehoon Kim, Xiao Chen, S. K. Banerjee, “Growth of Relaxed Silicon Germanium Structure by RTPCVD,” Electrochemical Society Meeting (Sub. Division of Texas) 1999.

4. G. S. Kar, S.K. Ray, Taehoon Kim, S. K. Banerjee, N. B. Chakrabarti, “Estimation of hole mobility in strained Si1-xGex buried channel heterostructure PMOSFET, ” Solid State Electronics, Vol. 45 (2001), pp.669-676.

5. S. Banerjee, D. Kim, Taehoon Kim, L. Weltzer, Y. Liu, S. Tang and M. Palard, “Nanoparticle Floating gate Flash memories,” Invited paper, DRC 2004.

6. Dong-Won Kim, Taehoon Kim and S. K. Banerjee, “Memory Characterization of SiGe Quantum Dot Flash Memories with HfO2 and SiO2 Tunneling Dielectrics,” IEEE Trans. Electron Devices, Sep 2003.

7. Dong-Won Kim, Prins, F. E, Taehoon Kim, Sungbo Hwang, Lee C.H., Dim-Lee Kwong, Banerjee S. K., “ Reduction of charge-transport characteristics of SiGe dot floating gate memory device with ZrO/sub 2/tunneling oxide,” IEEE Trans. Electron Devices, Vol. 50, Issue 2, pp.510-513, Feb 2003.

8. Dong-Won Kim, Prins, F. E., Taehoon Kim, Dim-Lee kwong, S. K. banerjee, “Charge retention characteristics of SiGe quantum dot flash memory,”2002 Device Research Conference (60th), pp. 151-152 of Conf. Digest.

9. Taehoon Kim, Chad Wang, David Onsango and S. K. Banejee, “Hole Mobilty Measurement in Compressively-Strained Si1-x-yGexCy Buried Channel PMOSFETs.” Solid State Electronics under revision.

10. Dong-Won Kim, Taehoon Kim, Yueran Liu, Lisa Weltzer and Sanjay K. Banerjee, “SiGe quantum dots memory devices with HfO2 tunneling oxide,” 2003 Device Research Conference (61th), pp. 131 of Conf. Digest.

Contact this candidate