RAJAGOPAL S Mobile: +91-895*******

E-mail: ak9y6z@r.postjobfree.com

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CAREER OBJECTIVE:

To obtain a position as a Physical design engineer with provision for innovation and creativity in a growing and quality-focused organization for getting a right start and quality exposure.

EDUCATION:

Advance Diploma in ASIC Design in RV-VLSI Design Center, Bangalore.

B.E (Electronics And Communication) from MIET Engineering College.(2011)

CORE COMPETENCY:

ASIC flow with emphasis on Physical Design

Static Timing Analysis & Synthesis

Full Custom Flow: Standard Cell Design

Digital system design and verification using Verilog

Logic Design

Working on Linux environment

SKILL SETS:

Hands-on experience with Standard cell layout design for 90nm technology

-Review of Foundry Document (JAZZ)

-Experience in drawing Compact Layouts with minimal Parasitics.

-Good Understanding of Layout Optimization& Physical Verification Flow.

-Area Reduction Strategies and Techniques to work with Layout tools.

-LVS Report Interpretation and Debugging.

Experience with transistor level circuit simulators.

Good understanding of DRC Rules for the given technology library

(Experience with JAZZ).

Experience in design and verification of digital systems with Verilog.

POSITIVE TRAITS:

Optimistic.

Adaptable to work environment.

Committed to the responsibilities.

EDA TOOLS:

Prime Time (STA)

IC_shell from synopsys (PHYSICAL DESIGN)

Design Compiler (SYNTHESIS)

Calibre

IC Studio

Questasim

QUALIFICATION DETAILS:

Examination Discipline/

Specialization Mentor Institution Board/

University Percentage

B.E.

(2007-2011) ECE MIET Engineering College Anna University 76.06

XII Std.

(March 2007) Science+Maths R.C Higher Secondary School TN State Board 75.91

X Std.

(April 2005) ------ Arulneri High School TN State Board 88.4

PROJECT DETAILS:

SYSTEM DESIGN OF ALARM CLOCK:

Objective:To design a basic stop watch and add features to make it an alarm clock

Role:Design of RTL code and functional verification of the system

Challenges faced: designing the basic version of a system flexible for additional features

SYSTEM INTEGRATION OF UART:

Objective:To verify the functionality of various blocks of UART and integrate them Role:Verification of functional blocks and top level block design in RTL Challenges faced:Understanding and verifying the existing RTL codes of basic blocks

REVERSE ENGINEERING OF I2C: Objective:To reverse engineer an existing I2C coding & design a new one usingVerilog Role :Simulation of the existing interface and understanding the functional blocks Challenges faced:Understanding of the existing design in a different language (VHDL)

STANDARD CELL DESIGN :

Objective -Design of Basic Logic Gate Layouts with various Inputs and Drive Strengths

Role : Layout Design, Physical Verification & Back annotation for the above cells.

Spice Simulation of NAND , INVERTER,NOR, Netlists.

Tools Used: IC Studio, Calibre (DRC, LVS, XRC )

PHYSICAL DESIGN OF ORCA:

Role : Physical Design, Physical Verification, DFM, and BackAnnotation (Netlist to GDSII).

Tools Used: Calibre (DRC, LVS, XRC), Primetime, IC_shell from synopsys.

Summary : ORCA is a block level design. Learnt about different steps involved in the

physical design and verification flow. Understanding the various DFM issues.

PHYSICAL DESIGN OF I2C:

Role : Physical Design, Physical Verification, DFM, and BackAnnotation (Netlist to GDSII).

Tools Used: Calibre (DRC, LVS, XRC), Primetime, IC_shell from synopsys.

Summary : I2C is a block level design. Learnt about different steps involved in the

physical design and verification flow. Understanding the various DFM issues.

BE PROJECT:

FAST VIDEO PROCESSING FOR INFOTAINMENT APPLICATIONS:

Objective:To understand the ALTERA DE II kit informations and procedure to use.

Role :To write coding for I2C using verilog.

Challenges faced: Understanding and verifying the existing RTL codes of basic blocks.

Tools Used: Modelsim,Quartus II.

PERSONAL DETAILS:

Father Name : R Subramanian

Father’s Occupation : Businessman

Date of Birth : 20th June 1989

Gender : Male

Nationality : Indian

Marital Status : Single

Language Known : Tamil,English

Permanent Address : 240,Vadugapatti,

Melpoothakudi(p.o)

Viralimalai-621316

Pudukottai Dist.

DECLARATION:

I hereby declare that the above mentioned details are true to the best of my knowledge.

(Rajagopal.S)

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