RESUME

MANDULA SHYAMU

Mobile No: 072********,

E-mail: agbm0m@r.postjobfree.com

KPHB, Hydearabad,Andhrapradesh-500072.

Career Objective:

Pursue a high caliber career for a mutually beneficial and continuing relationship with the organization where the job responsibilities lead to an intellectually stimulating career path.

Education:

• Pursued PG-Diploma in DVLSI from C-DAC (Center for Development of Advanced Computing) with an Aggregate of 76.10% and year of passing is July, 2011.

• Pursued B.Tech (ECE) from TKR College of Engineering and Technology (JNT University) with an Aggregate of 67.67% and year of passing is June, 2010.

• Pursued Intermediate Education from ANDHRA PRADESH RESIDENTIAL Junior College (Board of Intermediate Education) with an Aggregate of 87.3% and year of passing is Mar, 2006.

• Completed Schooling from ANDHRA PRADESH RESIDENTIAL SCHOOL (Board of Secondary Education) with an Aggregate of 85.83% in SSC and Year of Passing is Mar, 2004.

Domain & Skills Details:

Product Domain Expertise: VLSI Design

Skills Category: Digital Design, ASIC, FPGA, CMOS Design

Languages: VHDL, VERILOG, C

Devices: Xilinx Spartan, Vertex

Tools: Riviera-PRO 2011.02, modelsim, Xilinx

Operating Systems: Linux, Win 9x/2000/XP, vista

Projects Undertaken:

Btech Main project

Title: Implementation of RC6 Cryptographic Algorithm

Company: PAN TECH SOLUTIONS (HIMAYATH NAGAR)

Description: RC6 algorithm is used for encryption of data in this project, which is designed to meet the requirements of advanced encryption Standard (AES). This project aims at the implementation of the RC6 block cipher using the VHDL and to have a fast encryption decryption engine. Encryption /decryption of the data are varied by VHDL simulator. A data which is in binary form has been demonstrated for encryption and decryption.

POST GRADUATE Diploma project

Title: Field Programmable Gate Array Implementation of Reed-Solomon Code, RS (255,239)

Company: C-DAC (Center for Development of Advanced Computing)

Description: This paper demonstrates an FPGA implementation of the Reed- Solomon, RS (255,239), and codec architecture for the OTN G.709. The RS codec is designed to occupy the least amount of logic blocks, be fast and parameterizable. I am presenting an efficient implementation of the encoder algorithm on reconfigurable devices in addition to a non-finalized version of the decoder. Both encoder and decoder are synthesized to Fpga's Spartan-3e.

IEEE projects

Title: An Efficient Implementation of Floating Point Multiplier

Description: This paper demonstrates an efficient implementation of an IEEE 754 single precession floating point multiplier targeted for Xilinx Virtex5 FPGA VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a multiply and Accumulate (MAC) unit. The multiplier was verified against Xilinx floating point multiplier core.

Title: An Improved Squaring Circuit for Binary Numbers

Description: This paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed.

Work Experience:

Total Experience: 1Year

VLSI Software Developer

PLANET SIGMA EMBEDDED SYSTEM PVT LTD - Hyderabad, Andhra Pradesh

January 2012 to Present

> IP Products Developing

>Projects Dealing

VLSI Lab Assistant-CDAC - Mumbai, Maharashtra

August 2011 to October 2011

> Dealing VLSI Design LAB

> Dealing VLSI Design Classes depending on STA, VHDL

Achievements:

• Won FIRST PRIZE in chess at B.tech level.

• Achieved MERIT STUDENT OF THE YEAR award two times in high school.

Extra Curricular Activities:

• organized various Technical events at college level (Prathibha, ECTA)

• Active participation in various cultural events held at college and school level.

Personal Profile:

Date of Birth: 05th June 1988

Gender: Male

Nationality: Indian

Father's Name: M BALANARAYANA

Languages Known: English, Hindi and Telugu

Hobbies: Playing chess, Listening music, Reading Books

Declaration:

I hereby declare that the details mentioned above are true to the best of my knowledge and belief.

Place: Hyderabad

Date: (M SHYAMU)

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