SUSHANTH REDDY KARMUNCHI

Fresno, CA ***** 559-***-**** admphx@r.postjobfree.com

Skills

● Programming Skills: C, Python, Verilog, Matlab, System Verilog

● Physical Design: Cadence Innovus, Floor planning, Placement&Routing, CTS.

● Tools: Cadence Virtuoso, Cadence Innovus, Synopsys DC Compiler, ModelSim, Hspice.

● Embedded Systems tools: Keil uVision, mbed Compiler

● Database: SQL

Education

Master of Science: Computer Engineering Expected in 08/2021 California State University - Fresno - Fresno, CA

Course work includes VLSI circuits and systems, VLSI Physical Design, Analysis and design of digital circuits, Computer Networks, Embedded systems.

● Elected to Vice President for Indian Student Club in 2019-2021 Bachelor's of Engineering: Electrical And Electronics Engineering 05/2016 Bangalore Institute of Technology - Bangalore

Microcontrollers, Digital signal processing, Linear IC's and Design, Logic Design, Analog Electronics circuits, Power Systems. Work History

Graduate Student Assistant 08/2020 to 05/2021

California State University Fresno – Fresno, CA

● Supported instructor with test administration, curriculum development and assignment grading.

● Assessed student assignments to check quality and completeness before submission for grading. Supported classroom activities, including grading, homework and reviewing exams.

Software Analyst 11/2016 to 04/2018

Capgemini Consulting Global – Bangalore, India

● Worked on .NET for making projects for clients like GE and PEPSICO. Used SQL for database and html for presentations and frontend using softwares like Microsoft Visual Studio Server.

● Worked in the IT section of the company to help fix bugs in company project teams. Analyzed project requirements to find bugs issues within a timely manner for clients like GE, PEPSICO Crafted graphics and animations using WPF, WCF, CSS to be used in interface and creating framework for service-based applications. Intern 01/2016 to 02/2016

Rail Wheel Factory – Bangalore, India

● Used to monitor PLC machines working and maintenance. Noted down readings of every machine from basic to the complex process of making wheels for railway for 200 wheels/day.

● Being Electrical and electronics engineering had also researched on the power grid section under the guidance of an assistant electrical engineer from the grid. Projects

DVFS controller for Multi Core system of Quadratic function

● Used a MUX to control two different clock cycles for 2 different cores having 8-bit FIFO stack each as an Injection and consumption application for the DVFS Controller.

● Used an Quadratic equation as the inject model to the 8-bit FIFO for two cores individually, passing on the input to the equation. Depending on the function to execute the quadratic equation every cycle, the MUX is used to control the clock cycles to power the cores. Physical Implementation of 8-bit shift register using Cadence Innovus

● The placement and routing of the shift register circuit are carried out in the Cadence Innovus tool using the 180nm library.

● Reporting power, area, and timing at each stage of Pre-CTS, Post-CTS, and post-routing of the circuit and GDSII file is generated. In Post-CTS the overall Power is abridged to 12.69mW, Area is 119.7 um^2 in 65nm CMOS Technology. 32-bit floating-point unit RTL design & 256-bit MAC unit in RTL design

● Floating point unit and MAC unit Verilog design in ModelSim, Synthesis in DC Synopsys obtaining a Total cell area of 12000 mm2 with positive slack time of 0.19ns.In addition, the multiplication and division module has the overflow, underflow features. Physical Design in Cadence Innovus to obtain the GDSII after place

& route for 65nm CMOS Technology

Transceiver design for CNN based Wireless Network on Chip

● An energy efficient wireless Transceiver is designed for application in Convolution Neural Network based Wireless Network on Chip architecture.

● The transmitter is designed in CMOS technology for non-coherent detection at the receiver end and in 16nm FINFET technology using HSPICE simulation tool to test the gains and Noise figure when compared with the CMOS technology under transient analysis. The feasibility of a differential BPSK modulator is investigated for this project. The full-duplex capability for this transmitter is also investigated. System on Chip (SoC) Design for Embedded Applications

● Build an embedded system to exercise the use of PIO peripherals interfaces with an FPGA based soft-core embedded system.

● To display increment and decrement in decimal digits when three different keys are pressed one after other .Programs were executed on the Altera DE2-115 Cyclone IV SoC board. This program displays a decimal digit on the green lights LED3-0 on the DE2-115 board. The other lights LED7-4 should be off. Polled I/O is used to read the Data registers of the KEY and SW ports to check the status of the buttons and switches Link Budget Analysis of OOK AND DBPSK Modulation

● Use of Matlab for plotting graphs to find out the gain and power output in dBm for the OOK and DBPSK modulations techniques and standards for multiple Antenna Directives, Frequencies, data rates and Distances.

● Determining the received power, to ensure that the information is received intelligibly with an adequate signal-to-noise ratio. For 100 GHz frequency, 16Gbps data rate, 10mm distance and 5db Antenna directive the receiver power was -20 dBm. Implementation of DOS attack on Raspberry pi

● Here Raspberry Pi is developed as a local web server. And a DOS attack script written in Python is executed to attack the Web Server and the website that was created using the LAMP method for Raspberry Pi.

● A website is developed using Wordpress showcasing different mitigation techniques for DOS attack. Also used Wireshark to monitor the incoming requests from the DOS attack

Speed and Auto Piloted Vehicular Bot

● Use of FRDM-KL46z board to design a speed and auto piloted bot in Mbed Compiler by integrating different sensors like Gyro and ultrasonic to an 3 wheel motor based vehicular prototype.

● The implementation is to maintain the angle of the bot slowing down, and to avoid obstacles by stop and steer process. Certifications

● IEEE - A. Bonasu, S. R. Karmunchi and N. Wang, "Design of Efficient Dynamic Scheduling of RISC Processor Instructions," 2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), 2020, pp. 0236-0240, doi: 10.1109/IEMCON51383.2020.9284902.

● CADENCE - Completed the Cadence Training Course Verilog Language and Application V26.0 https://www.youracclaim.com/badges/b672d64a-902f-40cd-80f0-1853fb583d1a?source=linked_in_profile Keywords: VLSI, C, Python, Verilog, Matlab, Cadence Virtuoso, Innovus, Synopsys, Compiler, ModelSim, Hspice, :RTL, Partitioning, Floor planning, P&R, Clock tree synthesis, Physical Design, ASIC, SoC, LVS, DRC.

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