Additional Experience:

NeuroTech at Berkeley Hardware Team Lead

• Manages funds, hardware infrastructure, and teaching material for the Hardware team

• Teach workshops involving circuit design

May 2019 - Present

Relevant Coursework:

• Hardware: ASIC Laboratory, Analog Integrated Circuits Introduction to Digital Design and Integrated Circuits, Microelectronic Devices and Circuits, Integrated-Circuit Devices, Instrumentation in Biology and Medicine, Introduction to MEMS

• Software/Theory: Great Ideas of Computer Architecture (Machine Structures), Signals and Systems, Data structures, Medical Imagining Signals and Systems Project Work:

• Designed programmable gain switched capacitor pre-amplifier and analog MUX in Cadence Virtuoso that was integrated into a class project’s mixed-signal processing chip in collaboration with other two student

• Four Stage CPU implementing the RISC-V ISA running with a clk period of .6ns post-PAR in Cadence Innovus

• Designed an NMOSFET, using Synopsys’ Sentaurus package, with a gate length of 25nm, Ioff of less than 150nA per micron channel width, and Ion of greater than 1.4mA per micron channel width

• Created a three-stage MOSFET amplifier with 50 gain and a ~350kHz bandwidth

• Voice-command car using PCA, K-means, and other control algorithms to recognize speech and move accordingly SDSU Smart Health Lab Summer Intern

San Diego State University

• Repurposed commercially available EMG, EEG, and EKG sensors/software into economical prototype medical devices paired with LabView in conjunction with graduate students EE16B Lab Academic Student Employee

University of California, Berkeley

• Facilitated the teaching of over 80 students in weekly lab sections on circuit design and control systems January 2019 - May 2019

Electrical Engineering Intern at HUMM

Berkeley, CA

May 2019 - July 2019

• Redesigned hardware for tACS neurostimulation device focused on inhouse production speed and component cost

• Designed several testing PCB boards in Eagle to test efficiency, compatibility and to verify concepts

• Created LTspice models of device and future output stage improvements Undergraduate Researcher at UCSF Henry Lab

• Cleaned and analyzed minute by minute data from FITBITs to develop statistical modeling techniques to understand the pattern of life for patients at varying stages of multiple sclerosis University of California, San Francisco

October 2019 - February 2020

Electrical Engineering Intern at Apple June 2020 - September 2020

• Collaborated with team to develop concept and schematic of a development platform based on an MSP432 microcontroller and Artix-7 FPGA

• Learned about and implemented communication standards and single-ended I/O standards such as SPI, I2C, UART, LVCMOS etc.

• Designed a power distribution system with buck, buck-boost, and LDO supplies centered around power efficiency and ease of implementation

• Worked cross-functionally with component engineers, vendors, and FPGA engineers to ascertain the best components and architecture for the device

adkvee@r.postjobfree.com • 858-***-**** • linkedin.com/in/kevmjung Education:

University of California, Berkeley

Major: Electrical Engineering and Computer Science BS GPA: 3.47 Class of 2021

Skills:

Hardware Design: Cadence Virtuoso, Verilog, HSPICE, LTSPICE, Eagle Coding: Python, Java, Scheme, C, LabView, Git, RISC-V Minor: Bioengineering

*currently deciding between admission offers for M.S. in Electrical Engineering [Fall 2021-Spring 2023] Work Experience:

May 2018 - August 2018

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