Strategic business development director

Peter Roy Ateshian

San Jose, CA

Professional Summary

● Entrepreneur with 19 years of experience in the Electronics, software, RTL HDL SoC and system design industry. Manage multinational team tasks successfully to meet all budgets and deadlines with margin. Innovative and adaptable leader with over 20 years’ experience developing, deploying, and evaluating engineering design and conducting operations monitoring and analysis to improve quality, cost reduction, and efficiency.

● Prompt Engineering: perplexity Groq Labs LPU groqchat chatGPT bard/gemini copilot RTL auto generation ML Naval Applications for Machine Learning since 2016

● ASIC FPGA DSP Analog circuit design

● UVM UVMF RTL HDL SV agent’s generator patterns factory new options monitor scoreboard coverage for code, functional, toggle, switch report analysis generation prior AVM OVM - AI-ML Augmented UVM

● Satellite communication RF laser optical

● High performance UAVS - Tactical Missile Design AARGM ER-AARGM Northrop Grumman Los Angeles

● Hardware acceleration of AI-ML algorithms and heuristics with RTL HDL DSP ASIC FPGA and GPU

● 16+ years’ experience with VHDL, Verilog, HLS-C and AMD/Xilinx, Intel/Altera & Microchip/Actel FPGAs HDL Verilog/System Verilog development experiences. Since 1992 for Oracle Exemplar Logic

● ARM - Wrote FPGA eBook for the US NAVY on FPGA ARM embedded design 2008. Technical troubleshooter skilled in identifying, isolating, and resolving complex issues.

● Leadership vision and strategy in research and technology domains for commercial and military clients DoD Clearances SAP TS SCI poly-CI S CUI

● Management experience - Track record of success coordinating and scheduling concurrent high visibility projects leading teams of 25–50 personnel specializing in various RTL HDL to ASIC VLSI Fab EDA & TCAD disciplines on three diverse continents.

● Strong Business Development knowledge in growth planning and contract negotiation.

● Accomplished communicator presenting capabilities to customers, speaking at technical conferences, and strengthening relationships across functions to drive strategic business operations.

● Several-year member of the Achievement Club for technical excellence and quota performance of over $2M.

● Directed technology in Initial Public Offering (IPO) and Mergers and Acquisitions

(M&A) activities for five successful technology startup companies.

● RISC-V SiFive RISC-V quad 64-bit FinTech 300K SLOC conversion Knowledge Decision Systems LLC San Jose

● Developed and published a U.S. Navy small satellite eBook on SmartFusion FPGA and mixed signal use entitled, “ARM Synthesizable SoC Design with Electrically Erasable FPGAs with Mixed Signal Applications”. RTL to FPGA

● Won an ISS Design Challenge 2016 for the design and deployment of a Femto satellite swarm for the next Internet of Space (IoS) and Intel Developer Forum (IDF) 2016 Internet of Space Femto Satellite award.

● Researched diamond substrates for thermal management in high-energy electronics with InP and GaN High Electron Mobility Transistors (HEMTs) for three phases of the STTR DoD funded research.

● Essential subject matter expert in completing four Intel ICG missiles RTL to GDSII projects for mixed-signal integrated circuit tape-outs with Calibre HLVS-HDRC nanometer Mentor Graphics EDA tool suite/CAPI-viafill, Star RC-Apollo Synopsys/Avant! Place, and Route/RC Extraction tool flows, which were evaluated as production quality on the first pass and used as a benchmark for future M&T/ICG references.

● Delivered an integrated circuits assessment of 100–75nm technology shrinks on K5-K9 RTL to GDSII microprocessor devices with Calibre Litho/PSM completing first-pass production silicon. Reduced runtimes from 15 hours to 0.27 hrs. (17 minutes) curing critical flow and netlist issues by using multiprocessor (turbo) modes.

● FinFET & Fully Depleted SDOI design Carbon nanotube complementary transistor circuits imperfection immune with selective etch DFM yield improvement. (Imperfection Immunity) Improved power speed product FoM.

● Completed over thirty RTL to ASIC, RTL to DSP, RTL/HDL to ARM Cortex SPARC x86 SoC designs. All are first working Silicon and 90% first production shipping silicon for the best times to profitability. Technologies ranged from 90nm to finFET CMOS logic with RISC-V FPGA emulation prototypes proving functional operations. RISC-V LLVM verification validation and test. Review Esperanto Glacier Point II ASIC minion maxion 1,088 RISC-V cores - required double precision floating point for FinTech application, core count and bandwidth reduction > 50%.

Analog Signal Processing Power converter:

● Design and implementation of analog signal processing circuits for various applications, including audio, communication, and control systems.

● Techniques for signal conditioning, filtering, amplification, and modulation.

● Selection and optimization of analog switched capacitor filter integrated circuits and components.

Power Conditioning:

● Design and implementation of power conditioning systems for various applications, including industrial, residential, and automotive.

● Power factor correction, voltage regulation, and harmonic mitigation.

● Selection and optimization of power electronic components, such as transformers, capacitors, and diodes.

DC-DC Converters:

● Design and implementation of DC-DC converters for various applications, including power supply, battery charging, and motor control.

● Types of DC-DC converters include buck, boost, and buck-boost converters.

● Selection and optimization of DC-DC converter components, such as transistors, diodes, and controllers.

AC-DC Converters:

● Design and implementation of AC-DC converters for various applications, including power factor correction, battery charging, and renewable energy systems.

● Types of AC-DC converters include single-phase and three-phase converters.

● Selection and optimization of AC-DC converter components, such as transformers, capacitors, and diodes.

SEPIC Converters:

● Design and implementation of switched-mode power converters (SMPS) commonly known as SEPIC converters.

● SEPIC converters are used in various applications, including power supply, battery charging, and LED drivers.

● Selection and optimization of SEPIC converter components, such as transistors, capacitors, and inductors.

Navy Civilian Military technology:

● GOOGLE GCP Clang, Golang, tensor flow image processing for IoT network.

● Awarded PhD student scholarship by the National Security Institute at the Naval Postgraduate School.

● RTOS C11 programming, Tactical Missile Design, DSP FPGA ASIC embedded SoC and PSoC multicore applications. Assertion, unit test, module test, subsystem test, verification and validation to DoD standard requirements. RTL Verilog/SV- OVM/UVM experience: agents, patterns, generators, sequencers, monitors, scoreboards with code functional toggle coverage for RTL to FPGA, RTL to ASIC, RTL to DSP multi core RISC-V ARM SoC and ip blocks design. RTL Cache controller for Coherence & Consistency MESI+ protocol

● AMD Xilinx RTL HDL to FPGA design and timing closure experiences: - FPGA Signal Processor DSP, DDR controller, RTL HDL Scatter Gather DMA controller design for DoD Contractors Northrop Grumman AARGM Missile program and US Navy Tactical Missile design - since 2006 unclassified video available upon request.

● Verification and lab bring-up: - Migration of Xilinx ISE14.7 RTL design to Altera/Intel RTL HDL ARRIA A10 SoC Quartus II SoC Pro 19.X - Libero RISC-V Polar Microchip then to ASIC HiFive SiFive quad 64-bit RISC-V SoC with Linux. Experience with RTL HDL Xilinx ISE 14.7 and Xilinx Vivado 2020.3 FPGA tool chains.

● Experience writing DOORS requirements and design documentation for RTL HDL DO-254 UVM compliant projects

● Experience with IBM DOORS FlowDown, Confluence, Jira, Bitbucket, Gitlab, HDL Designer

● Experience with MIL-STD-882E, 1553 and MIL-HDBK-516C RTP protocol IEEE 802.11/802.15 and working principles of VoIP clients, QCom wlan drivers. Technical Skills

● Systems: Integrated Circuits, Robotics, Rockets, Radars, Satellites, Databases, Prototyping, Logic, Machine Learning, Agile, Information Security, Networking, QPSK, Cloud Computing, Block Chain, Verification, ASIC

● Operating Systems / Software: Windows, Linux, UNIX, TinyOS, Minix, MATLAB, Python, C, C++, Ledger, Verilog, Cadence, Eclipse, Fortran, Vivado, ISE14.7, Quartus II Pro SoC, Libero, Smart Fusion, FGPA, Arria10, API, Pascal, ASP.NET, Pearl, Java, CAD, Coding, Vivado, Raspberry

● Hardware: SAN, Microprocessors, Blockchain Merkle tree ZKP Ethereum DLT IBM hyperledger RSA Homomorphic cryptography Encryption, RAM, Digital Signal Processing, Drivers, Electronics, SGI, Lasers, Imaging, Radios, Cameras, VHDL, VLSI, SUN Microsystems, VoIP

Professional Experience

Xtrm Designs, LLC., San Jose, CA 1992 – Present

ASIC Design Verification Engineer/Senior Principal Engineer machine learning Clients: Intel, AMD, Honeywell, Avantus Federal SDA USSF, Raytheon RTX RIS, Boeing SCS USAF, Amentum INDO-PACIFIC COMMAND Camp H M Smith, Draper Labs, Pulse secure Ivanti, Northrop Grumman Corp, ASML/Tech Mahindra/Cerium USA, KDS Global LLC, GCR CalTech JPL NASA and US NAVY

Oversee 50 employees and contractors in engineering design and evaluation, Business Development new and sustained development, EDA and CAD tools, sales, and services to provide technical consulting expertise to the U.S. Navy and Fortune 500 contracting and telecommunications companies. Provide IC design mapping to evaluate, recommend, implement devices, applications, technology for successful business and strategic decisions.

● New analog CMOS finFET op amp design ICMR and lower power specific requirements, RTL to ASIC Integrated Nuclear Event Detection INED circuit models.

● Prompt engineer LLM experience with Groq Labs LPU token architecture, Copilot, Bard/Gemini, OpenAI chatGPT, GroqChat RTL HDL and SV/SVA automated generation

● RISC-V finFET design proposals for military applications.

● Implemented AMD Y2K Calibre/IC rule corrections for CS19 to CS59 Tape Outs due to the opposite command EDA software code change.

● Using UVMF Siemens EDA Mentor Graphics Corp verification framework and RTL/HDL AVM, OVM Predecessor methods in several SoC integration & ASIC DSP mixed Signal SoCs.

● Working with System Verilog as an assertions tool for the verification of VHDL, HLS C and Verilog RTL HDL synthesizable logic. UVM OVM AVM Automation agents’ generators patterns factory new options monitors scoreboard report coverage, code, functional, toggle switch, controller & analysis

● Completed SUN Microsystems Gemini block conversions using Calibre HLVS and Simplex flows for RC extraction. CDC analyst.

● Used Arteris NoC route to protocol tools to a network processor back pressure capability to prevent buffer FiFo overflow from multiple clock Domains.

● Xilinx with Embedded Design Kit (EDK) Toolset: Xilinx Platform Studio (XPS).

● Systems-On-Chip (SoCs) Processors (PowerPC, MicroBlaze, Vivado, Zynq 7000-ARM) Virtex XC2-5.

● Intel's Altera Quartus II, Pro Prime Arria 10 HPS (embedded dual ARM Cortex A9) FPGA VHDL and Verilog Applications

● Hands-on experience with AMBA (now AXI*) in FPGA and multiple cores ARM based SoC integration ASIC designs.

● Supervised Learning applied to MIMO optical, Digital logic and mixed signal analog design with RTL Verilog / VHDL / System Verilog.

● Design custom Bit BLT GPUs and systolic array processing architecture.

● Delivered an advanced production solution to extricate flat GDS2 layers from a silicon ensemble, rebuilding with CheckMate when the Cheetah database was too large to allow hierarchical output.

● Assisted design groups in deploying Calibre to replace CheckMate/Hercules/Dracula in 13 processes ranging from EEPLD/Flash to RF-Bipolar, exceeding schedule by completing the project in only 11 months.

● Worked with RISC-V and RISC-V64 RTL HDL CCCP cache coherency and consistency MESI+ protocol. Added extra bits to know which CPU cores wrote and read the cache to prevent cache contamination.

● 1149.1 BFM (bus functional models) RTL/SoC RTL/ASIC RTL/FPGA Verification IP for UVM Methodology with Verilog/VHDL variants. FPGA ChipScope verification and debug.

● ASIC chip CPU Data path synthesis design and timing optimization.

● Exemplar Logic FPGA EDA RTL tool box for synthesis simulation of Verilog VHDL variants.

● QSound psycho-acoustic 3D sound DSP and ASP algorithms in Silicon CMOS implementation.

The Naval Postgraduate School WWW.NPS.EDU Monterey, CA 9/25/2006

-12/31/2023

Faculty Associate Research

Adjunct Professor

Develop and research technical courses to improve defense technologies, systems, and programs for military officers. Act as a STEM Mentor for interns. Teach ECE, systems engineering, and space science in hand-on labs and distance learning including interfacing with robotics, rockets, radars, and satellite communications.

Naval Applications for Machine Learning NAML NWIC San Diego since 2016 tensor flow TF-lite tensorflow lite IBM CWP Cognitive Wargaming Platform OpenCV YOLOx target acquisition algorithms tensor flow augmented RNN Sensor fusion Supported the Trident Warrior 2010 exercise aboard the USS Bon Homme Richard to evaluate sea-based Programs of Record technologies.

Launched two stage 22-foot rockets in the Mojave Desert. NPS won 1st place over NASA, Boeing, NavAir & other universities. Tactical missile design development and launch courses. Develop and Conducted ARM Cortex RTL to FPGA-based classes for programmable SoC design.

Presented Counter-Improvised Explosive Device (IED) briefings at the Foundation Fall Quarterly Event to provide information on the school’s research efforts and live demonstration courses.

Undersea wake detection and imaging with laser communication. Spatio-temporal 3D coding for MiMo FSO nLoS LPD LPE LPI laser communication enhancing soft error resilience for five domains and boundaries RFO dual optical RF detection imaging flash LiDaR

NPS Femto Satellite swarming constellation design and development with iridium transponder and IoT TRNG encryption. 2016 Intel Developer Forum- internet of space Femto Satellite swarming constellation design. HICSS 53/54 Spatio-temporal coded laser MiMo communication DoD RISC-V assessment study DARPA & NPS Esperanto 1024 core RISC-V architecture NAML NWIC San Diego 2017-2020 Naval application for machine learning algorithms Xtrm Designs LLC contracts:

Raytheon - RIS Polar/Geo El Segundo, BCT SDR FPGA, Colorado NASA JPL GCR Pasadena - EO/IR Modeling & Imagery Dataflow Automation Northrop Grumman - Tactical Missile Design AARGM ER-AARGM extended range KDS Global LLC - RISC-V64 HPC Fintech X86 code conversion Tech Mahindra - ASML contract

ICT, Inc. Vice President of Engineering

Parsec Software Vice President Sales & Applications 1983-1979

ATARI ASIC VLSI CMOS/NMOS Design Engineer

EG&G Reticon Analog Switched Capacitor Circuits & Filter Design Engineer Plantronics - DSP Cyclotomic & Switched Capacitor Filters EDUCATION AND CERTIFICATIONS:

The Naval Postgraduate School, Monterey, California, Coursework Toward PhD in Computer Science AI-ML LLMs and Systems Engineering 12/2024 (In progress) University Of California, Berkeley, California, Master of Engineering EECS and Business Administration, 1979

University Of California, Berkeley, California, Bachelor of Science, Engineering Science 1976 Tau Beta Pi, ETA Kappa Nu

SPIE OSA IEEE NPSF EDPS

ACTIVE TOP SECRET:

SAP / TS / SCI / CI-POLY / S / CUI DoD NASA USSF CLEARANCE 12/2023

Contact this candidate