Rohon Ray

**** * ***** **, ********, AZ *****

480-***-****, ad4fwn@r.postjobfree.com

Objective: I am currently seeking a job/internship opportunity to get involved in research or industry projects in the field of Digital/Mixed Signal IC Design and verification. I want to gain hands-on experience in different areas of Integrated Circuits such as Digital Design, Analog Design, and Mixed Signal design analysis. I believe Semiconductors will drive the world in the next 25 years and I want to be part of that exciting journey. US Citizen, No Work Visa or Work Permit required.

Education

Master of Science in Electrical Engineering-Mixed Signals Circuit Design Arizona State University GPA: 3.92/4.00 (Will be awarded on May 2024)

Bachelor of Science in Electrical Engineering (Awarded in March 2022) University of California San Diego

Minor: Biology (Awarded in March 2022) University of California San Diego Related Coursework Completed/Currently Taking:

● Machine Learning for Hardware Systems (EEE 598)

● Semiconductor Device and Process/Simulation (EEE 533)

● VLSI Architectures (EEE 526)

● Advanced Analog Integrated Design (EEE523)

● Computer Controlled Systems (EEE 591)

● Fundamentals of Solid State Devices (EEE 591)

● Semiconductor Device Theory (EEE 531)

● VLSI Design (EEE 525)

● Analog Integrated Circuits (EEE 433)

● Advanced Digital Project (ECE111), using System Verilog

● Digital Integrated Design (ECE165)

● Introduction to Computer Architecture (CSE141)

● Introduction to Computer Architecture Lab (CSE 141L)

● Components and Design Techniques for Digital Systems (CSE140)

● Digital Systems Laboratory (CSE 140L)

● Analog Integrated Design (ECE164)

● Introduction to Digital Signal Processing (ECE161A)

● Digital Signal Processing I (ECE161B)

● Filter Banks and Wavelets (ECE 251C)

● Fundamentals of Linear Systems (ECE101)

● Random Processes (ECE250)

● Electronic Systems and Circuits (ECE163)

● Advanced-Data Structures (CSE100)

● Analysis and Design of Algorithms (CSE101)

● Fundamental Device Materials (ECE103)

● Elements of Machine Learning Intelligence: Pattern Recognition (ECE175A)

● Semiconductor Physics (ECE135A)

● Electronic Devices (ECE135B)

● Linear Control Systems I (ECE171A)

● Computational Evolutionary Biology (ECE208)

● Introduction to Biophysics (ECE201)

Projects:

● Designing a FFT (Fast Fourier Transform) OVA (Overlap and Add) algorithm for fast Convolution Computations purposes using SystemVerilog (current project) Working with two other people, using System Verilog, we are implementing a 16-point FFT OVA algorithm and testing the speed of the algorithm in a pre-layout chip using DC compiler synthesis tool. Currently, we have designed all the required blocks for the FFT OVA algorithm (including the FFT butterfly module, the OVA module, and the ROM to store the twiddle factors). We also tested out the latency of each block design using ModelSim. and integrated all the blocks in our design (https://github.com/kaggar11/cnn_verilog)

● Implemented a 256x256 systolic array for depth-wise and pointwise convolutions for mobilenet (neural network) applications:

I designed and verified a scalable systolic array that can support both depth-wise and pointwise convolution using SystemVerilog. I have also designed and implemented a testbench to make the systolic array weight stationary so that convolutional computations can be supported. To do the pointwise and depth-wise mapping, I strategized with my partner on how the data would be the inputs into the systolic array, given an activation input image and a weight filter. My partner generated the text mapping files for activation input and the weight filter using pytorch/python scripts. The information for these files was stored in my implemented ROM.sv file. With the systolic array testbench, I generated a ROM instance that will read from the text files as well as a systolic array instance to do the convolution computations. For performance measured, we measured the latency of pointwise and depth wise convolutions. We found out pointwise convolution has a O(NxN) computation time for a given NxNxC input activation, where C is the number of channels. Depthwise convolution has a O(C x (N-K+1) x (N-K+1)) computation time for an NxNxC input activation image and a KxKxC weight filter.

(https://github.com/RohonRay123/EEE526Project)

● Single Ended NMOS folded cascode amplifier with a class AB stage: Using the Cadence design suite and tools, I designed a two-stage amplifier consisting of a folded cascode (with an NMOS input), and an NMOS/PMOS output stage regulated by a class AB circuit. I have also designed a wide swing biasing circuit for the class AB amplifier along with a beta multiplier. The purpose of the wide swing biasing is to get a better output voltage swing, and the beta multiplier helps in making the circuit less sensitive to temperature variations. The specs of the circuit were 80dB DC Gain, 1.5mW DC power dissipation, 10MHz unity gain frequency, input common mode voltage of 1V to 2V, 70dB PSRR, and CMRR with a (1pF 10kΩ) load. The circuit also has a 25 dB gain margin and an 80-degree phase margin with a 1uF load in series with a 1kΩ resistor.

● Modeling and Implementation of an unknown Pendulum System using Arduino and Simulink: Given an unknown pendulum system [voltage input, angle output] on Simulink, the task was to find out the system and design two types of control systems to regulate the pendulum system. The system identification of the pendulum was the first task of the project. To find the best-fitted transfer function of the unknown pendulum system, I designed a Simulink open loop of the pendulum with a Pseudo Random Binary Sequence (PRBS) Generator input. These inputs will be converted to voltage values by the Arduino for the pendulum system to understand. The open loop Simulink module was then downloaded onto an Arduino, which was used to gather the output. Afterward, I designed a System Identification MATLAB script with PRBS inputs, Angle Outputs, and a system order of the pendulum plant. The output of the script was the root mean square error between the actual Angle values and predicted open loop Angle values, as well as the parameters of the given system order. The order of the system was determined by an Order vs Root Mean Square Graph (When the RMS starts to saturate was the order of the system I took). After Identifying the Order of the system and the parameters, I designed a Discrete Proportional Integrator Derivative (PID) control for a closed-looped feedback pendulum system using Simulink. The purpose of a PID is to penalize all different error measurements of the system so that the output of the feedback loop can follow the input change. The feedback module system was then downloaded on the Arduino Circuit to verify PID’s performance. The other control system I implemented was the LQG (Linear Quadradic Gaussian) Regulator of the pendulum system. The purpose of the LQG is to minimize the cost function of the feedback pendulum system. The cost function depends on the feedback input (PRBS values), output angle, and Q, and R matrices. Q matrix penalizes the error states of the system while the R matrix penalizes the control bandwidth of the system. Like the PID controller method, the LQG regulator was downloaded onto the Arduino board to verify the performance.

● ASIC Acceleration for Graph Convolution Neural Network: I have implemented a neural network using the Digital flow design. The input data were 96 features for a graph of 6 nodes (6x96 matrix), input weight data in each dimension for three labels, and compressed data for the adjacencies for the nodes in a graph (given in a Coordinate form (COO) to represent sparse data). The output is the labeling of the nodes in the graph, which I implemented on System Verilog (RTL). In the next step, I created a script to convert my RTL implementation of a Neural Network into a synthesizable gate-level netlist. The script was run on Design Compiler Synthesis, which converts my behavioral RTL netlist into a structural gate-level netlist. Afterward, I used Innovus, which is an EDA tool to do automatic place and route. This converts my synthesized gate netlist into a chip layout. In Innovus, I performed RC extraction, and clock timing analysis to check for setup and hold time violations. Based on the data, I set my chip to work at 1.4GHz frequency with no setup time violations and no hold time violations. From the layout, I calculated the area of my chip to be 0.247mm^2 with power rings and 0.0675mm^2 without power rings. The power consumption was 18mW from the Innovus Power Report. I then created a netlist file APR file Innovus (Verilog file). This file was simulated on ModelSim and the latency was 9.45ns.

● Implementation of Low Dropout Regulator in Cadence: Using cadence, I designed a feedback amplifier that regulates the output voltage. The first step of the project was to design an amplifier, which needed a 40dB DC gain, a bandwidth of 200kHz and consumes less than 0.3mW of power. This amplifier will drive a PMOS, which will regulate the output voltage at its drain end to be 1.6V. The second step of the project was finding out the optimal size of the PMOS device that can handle from 1mA to 50mA of current without much change to the output drain voltage. To test the PMOS device, I used a 1V gate test voltage and a 1.6 Drain Voltage. I had to size the PMOS device such that it was able to tolerate 1mA to 50mA of current while having the drain output of the PMOS be at 1.6 V. I swept the (W/L) of the 300nm Length PMOS device and measured the current on cadence. I was able to find that (W/L)=6k will give a current of 50mA and hence I decided on that sizing. Afterward, I sized two resistors to feedback the signal to an amplifier and tested out the ripple voltage percent (highest output voltage percent change with a given current input ramp from 1mA to 50mA). The design had a 9% ripple voltage.

● Bitcoin Hashing using System Verilog (FPGA): The first part of the project was to implement an SHA-256

(Secure Hashing Algorithm) encoding algorithm using System Verilog. Given any input message, it would output a 256-bit encrypted message using various encryption steps. This would be useful to secure data and compress data, as even the smallest change in the input message can drastically change the output message. The next part of the assignment was to implement a blockchain that can store and secure any type of information such as financial transactions or medical records. The first block will include the data information of the first transaction and contain a signature, which is an SHA 256 encoded message of the first transaction’s data. The second block will contain data from the second transaction, as well as the signature of the first transaction block. The signature of the 2 nd

block

will be the SHA 256 encrypted message. The third block contains the data of the third transaction as well as the signature of the second block and continues so on and so forth. Quartus Prime was used to synthesize and simulate the RTL implementation of the SHA-256 blockchain encryption. The timing analyzer tool on Quartus Prime was used for a slow,900mV,100C process on an Arria II GX EP2AGX45DF2915 Device. The max frequency was 157 MHz, the latency of the RTL design was 273 clock cycles (50 MHz clock) and the number of LUTs used was 14,291.

● Designed a reduced ISA (Instruction Set Architecture) for encryption/decryption: Designed a reduced 9-bit Instruction Set Architecture (ISA) for the purpose of creating an LFSR encryption/decryption algorithm. Computers do billion of computations per second and they only understand binary values given in either as a 32-bit or 64-bit instruction set. By creating a 9-bit instruction set, it can effectively reduce the amount of memory a computer needs to store a set of instructions. Using RTL viewer, the ISA system Verilog Code was successfully synthesized. After designing an ARM-like Assembly Language to implement the LFSR (Linear Feedback Shift Register), a python script was implemented to convert the ARM-like Assembly code to a file of 9-bit instructions. This 9-bit instruction file was then used by the System Verilog Program to encode and decode messages.

● Design an 8 Bit Kogge Stone Adder: Using CAD software called Cadence Design Suite, the goal of this project was to find a faster, more efficient, low-power, algorithm that can compute the addition of two inputs of 8-bit numbers. The algorithm implemented was called the Kogge Stone, where pre-computed information based on the inputs of the program is used to generate another layer of information. Given n-bit inputs, the number of layers generated is log(n), which reduces time delay and increases the speed of the circuit. Three hierarchical architecture levels were used to design this program in Cadence: the transistor levels using PMOS and NMOS, Gate level design, and test bench was developed. Afterward, parasitic capacitance extraction was done to ascertain the speed of the Kogge Stone Adder to work till 3.5GHz clock frequency.

● Designed a Differential Amplifier Using Cadence Design Suite: Using Cadence, I designed a small signal amplifier composed of NMOS and PMOS transistors. The objective of creating an amplifier was to meet various specifications such as having a DC Gain of 70 dB, Unity Gain bandwidth of 30 MHz, Gain Margin of 15 dB as well as a Phase Margin of 65 degrees. This amplifier was supplied by a 1.8 V source and had a load impedance of 10pF. The simulation for this Small Signal Amplifier was done in a 25 degrees Celsius environment and used 0.18 um CMOS technology. This OTA is a Cascode load with a common source amplifier. To satisfy the Gain Margin and Phase Margin, I used a compensation capacitor. A bias network was also developed to bias the transistors for proper operation.

● Implemented a Bootstrapping and Model Selection Algorithm (Python/Bioinformatics): I have Implemented Felsenstein's tree-pruning algorithm for computing the (log-)likelihood under the General Time Reversible (GTR) model given a tree with known branch lengths and topology. The algorithm was implemented in Python and predicts the most likely model by creating artificial normalized distributions given the model parameters. Work

• Rambus-Internship for Digital IC Design (June 1

st,

2023 to September 15

th,

2023): I have worked on

developing an RTL code and synthesis/place and route for a third-order Sigma Delta Modulator to be used in fractional PLL.

• NCMIR-National Center for Microscopy and Imaging Research, Computer Programmer, May 2019 to July 2019

During the 10-week period of this program, we used CDeep3M cloud software to image process certain types of neuron cells. Moreover, I also designed plug-ins (algorithms) to assist in image recognition and analysis of different types of neural cells as well as parts of a neuron cell using the programming language Java. I worked under Dr. Daniella Bossa during my 10 weeks at NCMIR.

• Ma Sarada Hospital (India) Internship, Dec 2019 to January 2020 as Clinical Intern: I have worked as an intern in the Incentive care unit in a hospital in Kolkata, India, and shadowed doctors/nurses in their daily work and attended, witnessed, and helped the medical crew in performing different kinds of medical procedures such as catheterization, biopsies, intubation, Central Line, Ventilation Initiation, TMP Procedure

(Total Productive Maintenance). I was in the Surgical room many times and observed different kinds of surgeries like the removal of a toe of a diabetic patient. I also participated in caring for patients before and after surgery, Monitoring ICU patients' Blood pressure, Pulse, Temperature, and other vital parameters daily 3 times a day. I also read medical reports and the history of patients to fully understand their conditions and discussed with attending doctors and tried to understand the rationale behind the treatment administered to the patients. I learned a lot about the general working of hospitals, acquired hands-on medicine field experience, and learned about medicines, and procedures under the guidance of top-notch doctors like Dr. Sovan Chatterjee (Internal medicine), Dr. Modak (Residential Medical Officer), and Dr. Abhishek Biswas

(Surgeon) of Ma Sarada Hospital Pvt Ltd in India

Technical Skills/Qualifications

• Handling of Basic Engineering Lab equipment for the Engineering 101 course offered by the University of Arizona, AZ

• Computer Programming in C++, System Verilog, Java, MATLAB, Python

• Proficient in Microsoft Word, Excel, and PowerPoint.

• Proficient in Google Docs and Google Excel

Other Skills

● Enjoyed Leadership Roles and also worked well independently or as part of a team.

● Detail-oriented, analytical, a troubleshooter and problem solver

● Customer service experience, enjoy working in a culturally diverse environment.

● Excellent communication and presentation skills.

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