David R. Lindley

*** ******* **

Georgetown, KY *0324

ad2lt0@r.postjobfree.com

662-***-****

Overview

I have broad experience managing R&D projects from conception to sales including visiting customers to determine their needs, developing bottoms-up schedules to meet top-down constraints, leading product, test, and manufacturing groups in multinational cross-functional teams, driving the design schedule, and presenting technical status to upper management.

I am proficient with Jira, Confluence, Microsoft's Office tools (Project, Visio, Excel, Word, and Powerpoint), and various design entry tools / simulators. I have a working knowledge of Python, C, Linux, SVN, Sharepoint.

I am a certified SAFe Scrum Master, Agilist, and Product Owner/Product Manager. Detailed Work Experience

Infineon Technologies, Kentucky Design Center

Lexington, KY August 2022 – December 2023, Lead Principal Design Engineer

• Program Manager for the System Resource Subsystem group. Duties include managing multiple concurrent integrated circuit IP projects, scheduling new IP projects, and leading Cross Functional Teams from KY, CO, CA, Germany, Israel, and India.

• Scrum master for U.S. based team daily standup meeting and sprint planning.

• Hiring coordinator for group. Reviewed resumes, conducted initial phone screen, scheduled remaining technical screens, collected evaluations, and worked with HR to make offers.

Cubic / GATR Technologies

Huntsville, AL July 2019 – August 2022, Engineering Program Manager

• Program Manager and Scrum Master for electronic assembly R&D. Products included a 1.3m rigid satellite communications terminal, inflatable ray dome inflation unit, and mud box modems. Duties included status presentations to management, developing and tracking budget, developing the iteration plan during the iteration planning process, leading the sprint planning, scrum master of the daily standup meetings, reporting weekly status, and quarterly deep dive presentation to management. Budget was approximately $3M / year.

• Product Engineer for GATR modems. Created over 120 ECOs to the four drawing packages to make the modems production ready. Drove the ECOs through the PLM cycle and into production. Interfaced with both the internal production team and external sub-contractors to build first articles and production units.

• Led a production team during the 2020 COVID outbreak to deliver $1M order of GATR 1050 modems. Duties including directing/participating PCB debug, unit assembly and debug, QA, and final unit test.

Cypress Semiconductor, Colorado Design Center

Colorado Springs, CO July 2014 – July 2019, Principal Electrical Design Engineer

• Program Manager for the System Resource Subsystem group. Duties include creating and tracking design schedules for multiple concurrent IP projects, leading Cross Functional Teams from Japan, CO, CA, WA, Israel, and India, and hiring for the group.

• Program manager responsible for taking three integrated circuits from first silicon to qualification and production. Duties included managing world-wide Cross Functional team, managing schedule, and writing / presenting program reviews to Executive Staff.

• Hiring coordinator for group. Liaison with University Colorado Colorado Springs. Page 2 of 3

Camgian Microsystems

Starkville, MS 39759 February 2009 – July 2014, Senior Technical Staff

• Product Manager for Quantus Tank Level Monitor. Duties include customer support, interfacing with Design on current generation designs, and creating specifications for next generation products.

• Developed manufacturing plan and cost calculator for unattended ground sensor product.

• Managed design team developing PCB set for next generation unattended ground sensor. PCB set consisted of Antenna board, RF board, and Digital board.

• Developed next generation mixed signal PCB architecture to combine digital, mixed signal, and RF circuits onto one PCB. Circuit placement was optimized such that different sub-circuits would not interfere with one another. The architecture was a first pass success.

• Laid out various Digital, RF, and mixed signal Printed Circuit Boards (PCBs).

Cypress Semiconductor, Southeast Design Center

Starkville, MS 39759 June 1994 – February 2009, New Product Program Manager

• Program Manager for I/O IP Center of Excellence. Concurrently managed multiple I/O projects on various technologies.

• Program Manager for new SONOS NVSRAM core macro. Managed remote team developing first 130nm SONOS core compiler. This compiler enabled the architecture platform for 15+ years of successful SOCs.

• Program Manager for 130nm technology tapeout. Reticle set had multiple test chips from multiple worldwide design teams. Managed requirements and schedules from each team. Reticle set was Cypress’ most complex to-date at time of tapeout.

• Program manager for multiple Dual Port SRAM ICs from conception to production. Duties included project scheduling, weekly reporting, writing / presenting reviews to management. Directed cross function teams involving CAD, Marketing, Applications, Product, and Test Engineering.

• Hiring liaison for Louisiana State University. Traveled each semester to career fair and on-campus interviews. Also member of office on-site interview team. Provided training to new hires.

The Institute for Technology Development, Advanced Microelectronics Division

Jackson, Mississippi, February 1989 - June 1994. Computer Engineer.

• Member of engineering teams that developed mixed signal ICs for major industry customers. Duties included everything from fault analysis on a mixed-signal ASIC to design/layout/verification of mixed signal chips.

Department of Defense

Fort Meade, Maryland, January 1988 - January 1989. Electronics Engineer.

• Member of mega cell development team that designed the RAM and ROM megacell generators included in the CMOSn Standard Cell Family. Held TSSI clearance.

Education

• 1989-1995. Mississippi State University. Completed 15 credit hours of course work in Electrical Engineering graduate studies.

• 1983-1987. Mississippi State University. B.S. Computer Engineering. Page 3 of 3

Patents

• Multiple Sensor Data Processor Interface And Relay. Patent Number 201********. November 26, 2015

• Method and Apparatus for Dynamically Detecting Environmental Conditions and Adjusting Drive Strength in Response to the Detecting. Patent Number 8,271,810. September 18, 2012

• Address Counter Test Mode for Memory Device. Patent Number 6,813,741. November 2, 2004

• Electrical ID Method for Output Driver. Patent Number 6,353,336. March 5, 2002

• Address Counter Test Mode for Memory Device. Patent Number 6,078,637. June 20, 2000

• Data Transition Detect Write Control. Patent Number 5,751,644. May 12, 1998

• No-Bond Integrated Circuit Inputs. Patent Number 5,675,178. October 7, 1997

Publications

• Dillon, J. and D. Lindley. January 1, 2002. Discrete Memories Trade Off with Asic Cells. EE Times Online. Issue #14151.

kills

Accountability, adaptability, agile methodologies, analytical skills, awareness, budgeting, CAD, clarity, collaboration, commitment, communication, confidence, conflict management, coordination, cross-functional team leadership, data analysis, dependability, empathy, engineering management, enthusiastic, flexible, friendliness, goal setting, honesty, initiative, integrity, international teams, leadership, mediation, multitasking, negotiation, open minded, organization, planning, prioritizing, problem solving, professionalism, program manager, remote team management, respect, responsibility, self-motivation, strong work ethic, teamwork, time management.

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