ABHINAY RAJ KALAMBUR SABARAJAN

Phone: 716-***-**** Email: acwd46@r.postjobfree.com Santa Clara, CA - 95051

LinkedIn: www.linkedin.com/in/abhinayrajks

PROFESSIONAL SUMMARY

Results-driven Electrical Engineering professional specializing in semiconductor physics and VLSI/ASIC design, with an extensive background in project coordination and design processes.

EDUCATION

MS IN ELECTRICAL ENGINEERING Aug 2014 – Feb 2016

University at Buffalo, the state university of New York, GPA: 3.53/4

BE IN ELECTRICAL ENGINEERING Sep 2007 - Aug 2011

Anna University, Dhanalakshmi College of Engineering, GPA Equivalent: 3.2/4

Relevant Coursework: Introduction to VLSI/ASIC Design, Microfabrication Lab (Clean room experience), Computer Architecture, Solid State Device Physics, Analog Circuits, HDL Based Programming, Electronic Devices & Circuits, Introduction to Microprocessors (Microarchitecture & Assembly Programming), Digital Signal Processing, Digital Logic Circuits.

WORK EXPERIENCE

NANGATE, INC Santa Clara, CA

Physical Design Intern May 2016 – Present

Designed the universal gates and Flip-flops in Global Foundries 28nm Library from Netlist to GDSII/Layout design using CAD tool flow methodology.

Effectively created standard cell libraries (TSMC018) from Netlist to GDSII using Nangate library creator tool.

Migrated standard cells from 130nm technology to 90nm/180nm technology by efficient use of Perl/Python Scripts.

Physical layout design, DRC and LVS Verification and Characterization of universal gates, Flip Flops and standard cell components using Nangate Characterizer tool and Calibre DRC.

UNIVERSITY AT BUFFALO, NEW YORK Buffalo, NY

Graduate Teaching Assistant Aug 2015 - Jan 2016

Effectively handled Analog and Digital Design Labs for an undergraduate class of around 50 students.

Developed SKILL scripts to update schematics and Layout in Cadence Virtuoso and to convert layout to GDS files.

Efficiently managed the student group and successfully assisted them with their RTL based design projects.

INFOSYS LIMITED Chennai, India

Senior Software Engineer, Software Engineer & Software Engineer Trainee Mar 2012 - Jun 2014

Spearheaded the development of large applications that helped in improving the productivity effectively.

Coordinated with multiple teams, both onsite and offshore, to develop applications to clients as per their requirements.

Successfully managed several upgrade processes in client’s server that reduced job failures in production environment by 45%.

Received Awards of appreciation from Clients and my project manager for my diligent contribution in writing scripts using Unix,

Python and Perl that helped in improving the business significantly.

PROJECT EXPERIENCE

FULL CUSTOM IC DESIGN OF 3-TAP 4 BIT FIR FILTER Aug 2015 – Dec 2015

Implementing the schematic and layout design of the FIR filter in Cadence Virtuoso using 45nm technology.

Aimed at reducing the bottlenecks in filter performance by inserting truncation logic and improving the critical path delay by using multiple pipeline stages. Primetime was used to analyze timing characteristics

Floor Planning, placement and routing, power planning and RC extraction done using Synopsys ICC.

IMPLEMENTATION & VERIFICATION OF DDR3 DRAM CONTROLLER USING VERILOG Oct 2015

This project is aimed at designing an arbiter for DDR3 DRAM using Verilog programming language.

Heavily optimized with burst chop 4(BC4) read command, write and refresh commands and synthesized on XC6SLX25 FPGA in -2 and -3 speed grades using Synopsys Design Compiler tool and verified using VCS.

DESIGN OF 32 BIT MIPS MICROPROCESSOR USING CADENCE IN 45NM TECHNOLOGY. Feb 2015 - May 2015

Designed a 32-bit MIPS microprocessor with 32-bit SRAM cache memory, Decoder, ALU unit with registers.

Analyzed the effect of duty cycle at various pipeline stages and designed an Aging Aware Instruction Set Encoding model using Simplescalar that gives an optimum value of duty cycle and reduced the circuit delay by 52%.

FULL CUSTOM IC DESIGN AND PERFORMANCE ANALYSIS OF 6T SRAM USING CMOS AND DUAL TRANSMISSION GATE ADIABATIC LOGIC (DTGAL) TECHNIQUE IN CADENCE. Sep 2014 - Dec 2014

Sense amplifiers and Precharge circuits of SRAMs are designed using CMOS and DTGAL techniques to understand power & stability trade off.

Simulations of DTGAL based SRAM showed 47% reduction in power and 35% reduction in stability than CMOS based SRAM.

Floor planning, placement and routing done using Cadence Encounter tools.

CORE SKILLS

Cadence Encounter, Synopsys Design compiler

Cadence Conformal, Mentor Calibre & Primetime

Hardware Descriptive Language (Verilog, VHDL)

ICC, ModelSim, VCS

CAD tool Flow Methodology

Liberty, Power & Timing analysis & Extraction

DRC and LVS verification

CVS, SVN, GIT, Perforce

Object Oriented Programming using C++ and Java

C, Python, Perl and Unix

Physical Design flow

OS: Windows and Linux

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