TulikaRanjan

(*st Floor, #***,**th Cross, **th Main,BTM 2nd Stage Bangalore –560076)

Email: acvsy7@r.postjobfree.com Ph. No.: +91-974*******

acvsy7@r.postjobfree.com +91-968*******

OBJECTIVE

Seeking a challenging and rewarding opportunity in the field of VLSI Design and Verification, where I can contribute to organization success, learn and improve with new technology while being resourceful and innovative.

PERSONAL SUMMARY

2 + years months of experience in Digital Design Verification and implementation mainly in SOC based systems (Including 7 months experience at client location).

Experience in RTL Design verification and validation, test cases and testbench development

Good Knowledge of VHDL and Verilog

Good Knowledge of MATLAB /Simulink

Knowledge of Assembly languages programming, System Verilog HDL and UVM

Programming skills in C, C++

Experience in Aerospace domain and knowledge of DO-254 process.

Experience in Functional Testing, Regression Testing, System Testing and Performance Testing.

Ability to learn new technologies and Strong analytical skills

SKILL SET

HDLs : VHDL, Verilog, System Verilog

FPGAs : Spartan 3E, Actel, Lattice

EDA Tools : Xilinx ISE 10.1/14.2,Mentor-Modelsim, VCS 2014.12,

Actel Libero IDE,Magic Layout tool, Ng-Spice

Other Hardware Exposure :Processor 8085,Processor 8086, Microcontroller8051

Software Languages : C, C++, Perl

Mathematical Tools : Matlab

Configuration Management Tools: MKS, DOORS

Protocols :Modbus, RS-485,I2C

Methodologies :UVM

ACADEMIC PROFILE

Degree

Institute / University

Year

CGPA

M.Tech [VLSI Design]

National Institute of Technology (NIT-K),

Surathkal, Mangalore,

Karnataka

20010 - 2012

7.03/10

B.Tech [ECE]

Sikkim Manipal Institute of Technology,

Rangpo East Sikkim,

Sikkim

2009 - 2005

8.19/10

ACHIEVEMENTS

1.Received excellent performance award for delivery in HCL Technology Ltd. during the quarter 2015

2. Secured 98.6 percentile in GATE– 2010

3.10 GPA holder in 8th semester of B.Tech

4. Secured 23rd rank in UGET entrance examination – 2005

WORK EXPERIENCE

Currently working as a Software Engineer with HCL Technologies Ltd, Bangalore from Jan 2014till date.

PROJECTS

1.I2C protocol for IP Verification project

Description

Responsibilities

Technical Environment

HCL Internal Re-usable Master-Slave I2C VIP project involved in IP verification of I2C protocol which is serial communication protocol that allows multiple slave to communicate with one or more masters.

As Team Member my responsibilities includes planning, reviewing of Testcase,

writing handler to model driver of I2C protocol as master with monitors including assertion.

VCS 2014.12, HDL-System Verilog, Methodologies UVM 1.1, GIT- Configuration Management Tool

2.Parker_GlobalIIM_MCE_FW_Verif Aerospace project

Description

Responsibilities

Technical Environment

Parker Aerospace Bombardier Global 7000/8000 project involved in hardware verification and validation of the Flight Control System (FCS) which provides control and monitoring of all primary and secondary flight-controls.An MCE FPGA exists in the FCS as the means for an FCS REU (Remote Electronic Unit) to control an electro-mechanical actuator-channel. The function of the MCE FPGA (installed on the MCE control board) is to provide an interface between the Motor Control Electronics (via a Motor Control Data Link) and the Remote Electronics Unit (REU) and REU-related hardware on the Control Board.

As Team Member my responsibilities includes planning, reviewing of Testcase and generating HW verification report; Development, Simulation, Timing- Simulation, execution and debugging of simulation test scripts which include MCDL protocol duplex module (RS-485 duplex) and TestPort module for examining correctness of different module involved in MCE FPGA with fault monitoring,Reporting problem issues of bugs found in design and debugging timing simulation.

It also includes DOORs updates, Configuration management MKS updates and generating DO-254 compliance matrix such as trace matrix, Simulation review report, HVC report,Error and warning report and Problem issue report. Achieved SOI levels -2 for Global 7000/8000 flight with teammates

Modelsim PE Simulator, HDL-VHDL, Process followed - DO-254, Configuration Management Tool- MKS, DOORS, Device- Lattice.

3.UTAS_GECFullfillment_FPGA_Dev Aerospace Project

Description

Responsibilities

Technical Environment

UTAS UTC Aerospace project involved in hardware verification and validation of the military Flight Control System that include Monitoring, Controlling and Peripheral FPGAs for monitoring, controlling and interfacing of flight controls. Collectively called Motor control board system.

As Team Member my responsibilities includes planning, reviewing of Testcase and generating HW verification report; development, execution and debugging of simulation test scripts, sequencer and Handler which includes MODBUS protocol duplex module, Fault management module and Hall Resolver module; reporting problem issues of bugs found in design.

It also includes DOORs updates, Configuration management SVM updates and generating DO-254 compliance matrix such as trace matrix, Simulation review report, HVC report and Problem issue report. Achieved SOI-2 level for A-350 flight and SOI-3 level for KC-390 with teammates

Modelsim SE Simulator, HDL-VHDL, Process followed - DO-254, Configuration Management Tool- SVM, DOORS, Device- Actel.

4.POLE ZERO LATTICE FOR ADAPTIVE MODELING (M.Tech Major Project)

Description

Responsibilities

Technical Environment

Pole Zero Lattice For Adaptive Modeling implementation is done with IEEE algorithms and new algorithms has been generated to improve and to provide stability monitoring as well as noise immunity in the design of a transfer function for signal processing and in their applications in a real time systemunder guidance of Dr. S V. Narasimhan (Emeritus Scientist, NAL, CSIR, Bangalore).

Noise improvement and Stability monitoring algorithms has been implemented and verified with ANC system. Adaptive filters used in channel equalization, echo cancellation, adaptive coding, noise suppression and Active noise control for modeling real system with fewer coefficient by using lattice structure that enables orthogonalization in IIR makes lattice filter to converge fast. By exploring the correlation property of signal and noise, Feed Forward ANC and Feedback ANC system is realized using lattice predictor based on Griffiths LMS, Feintuch’s IIR, Steiglitz and Modified Steiglitz Mc-Bride Griffiths algorithms.

Matlab, Modelsim PE Simulator, HDL-VHDL

5.TERM PROJECTS IN M.TECH.

Description

1.Quine-McCluskey digital Synthesis’ algorithm is verified in c-programming to

get minimal set of prime implicants and essential prime implicants .

2. Booth Multiplier (radix-2) in VHDL and dumping in FPGA kit with a inter facing.

3. 8 Bit gray code counter using pseudo Nmos technology in Digital IC design

with Ngspice and Magic software.

4. Verified D algorithm by considering a sample circuit using Matlab and Perl .

6.RAW DATA SIMULATION OF SYNTHETIC APERTURE RADAR (SAR)(B.Tech Major Project)

Description

Responsibilities

Raw Data Simulation of Synthetic Aperture RADAR (SAR)” is simulated,compressed and generated back to get original data under guidance of Dr. A Vengadarajan (Sc F, LRDE, DRDO, Bangalore).

Matlab programming is done to generate, simulate and to compress raw images captured during flight imaging.SAR produces high resolution two dimensional image sensor in remote sensing and generates high resolution aerial photograph after extracting through compress image.

7. WIRELESS MESH NETWORKS AT COLLEGE SMIT SERVING MBMS (Term Projects)

Description

Responsibilities

Wireless mesh networks is established among the labs of electronics & communication Department to provide multimedia broadcasting links and multicasting services under guidance of Dr. (Prof.) R Bera (HOD of EC department).

Matlabsimulink designing done for MBMS to improve point to point range of router to get better coverage for Multi media files transition and reception by using horn antenna, parabolic reflector,window netmeeting, tomato firmware and matlab.

WORKSHOP:

Participated in workshop at SMITtitled“Modern Computing Technologies” including topicsrelated to ES, RTOS, Nano Technology under guidance of prof. H. K. D. Sharma, prof. M. K. Ghose.

TRAININGS:

1.Successfully completed training at IIT Kharagpur, Titled “computer Network Management” during summer vacation 2007 at IIT KGP of duration “25 Days” under guidance of Prof. Rajib Mall, Prof. AnupamBasu, prof. BaniChatterjee.

2. Successfully completed training on 12th Feb 2016 at Synopsys, Titled “System Verilog Testbench” in Bangalore of duration “3 Days” under guidance of Trainer Mr. VinodCheedella.

PERSONAL DETAILS

Date of Birth : 26st Jan 1987

Passport No. :H7031317

Nationality : Indian

Languages : English,Hindi

TulikaRanjan

22thJune 16

Contact this candidate