Email : acvllm@r.postjobfree.com Contact No : 887*******,945-***-****.

PROFILE:

An Efficient VLSI Design Engineer with 4.3year experience (with 6month training from CDAC) in designing and debugging. Hands on experience on high speed interfaces, Micro architecture Design, Synthesiss friendly RTL Development.

SUMMARY:

4+ years of experience in design, development, and debugging of various applications like Broadcasting Encoders, AES based Digital Signatory device, Ethernet device supporting 1Gbps communication, Processor communication protocols.

Strong in Digital design, Micro-Architecture Design using VHDL, Verilog.

Waveform analysis &debugging skills using Chip scope, Signal Tap.

Worked on Ethernet, AMBA AHB/AXI, Ethernet, UART, and I2C.

Good Exposure of RTL Design, Simulation, Debugging, CDC.

Developed L2, L3 layers RTL Module for Video over IP.

Have Good knowledge of Video Broadcasting Domain (MPEG-2, Transport Stream PSI), DVB.

Experienced in Encryption Algorithms i.e. SHA1, RIJNDAEL.

Clear understanding of object oriented programming concept and Shell script.

Adept in Digital system design from requirement analysis to system study, designing, testing, debugging & documentation with cross-cultural teams.

SKILL MATRIX:

H/W Description Language : Verilog, SystemVerilog, VHDL, Assembly.

Embedded Processor : ARM.

S/W Languages : C, C++, Shell scripting.

EDA Tools : Xilinx ISE14.5, Vivado -2012, PlanAhead14.5.Model-SIM10.2, Quartus,

Questa-Sim, MATLAB-Simulink, TINA.

Network Protocols : UDP/IP/ARP/IGMP.

Environment : Windows XP/Windows7, Linux.

EDUCATION:

2012- Certification in VLSI from CDAC(PG Diploma in VLSI with 72.4%).

2011- B.Tech. In Electronics & Communication Engineering from Dronacharya College of Engineering, Greater Noida-DCEGN (Uttar Pradesh Technical University) with 64.7%.

2007- XII from R. S. Inter College, Aligarh (Allahabad Board) with 60.00%.

2005- X from R. S. Inter College, Aligarh (Allahabad Board) with 61.16%.

INDUSTRIAL EXPOSURE:

Working with HCL Technologies, Bangalore as Lead Engineer from (Apr2016).

Worked with Rakiya Information Technology Solutions as Senior Design Engineer(Jan2016-Mar2016).

Worked with Rudrakhsa TechnologyPvt. Ltd., Mumbai as a VLSI Design Engineer (Nov 2013-Dec 2015).

Worked with Sahasra Electronics Private Limited, Noida, as Production engineer (Apr2013-Oct2013).

Worked with Qualitat Systems. (Pune), as VLSI Design Engineer (Oct 2012 - Mar 2013).

PROFESSIONAL PROJECTS:

Title: Conversion of video stream Multi Program Transport Stream (MPTS) to Single Program Transport Stream (SPTS)

Role: Team Member

Details: Project was lead to convert MPTS to SPTS.This project was having 3 phases TS parsing, buffering and remaking of TS as required to any dedicated PID.

Responsibilities:

Involved in generating design specification on basis of ISO standard (IEC/ISO-13818-1).

Developed RTL Modules for PAT parsing.

Involved in development of PCR re-stamping module for correct clock generation at decoder end.

Developed Micro-architecture for design for project.

Language: Verilog.

Title: Video MPEG Transport Stream (TS) Analyzer.

Role: Team Member

Details: Core team was responsible to design TS Decoder for broadcasting product. Analyzer is a part of Decoder for analyzing TS and forward it to decode if stream is perfect as it required. All the PSI table Information is extracted and passed to particular buffers for particular service.

Responsibilities:

Involved in generating design specification on basis of ISO standard (ETSI-ETR 290 & IEC/ISO-13818-1).

Project is sub-part of major project TS Decoder including TS De-multiplexing, Parsing, PSI Table Management.

Developing RTL Module to convert Incoming serial data stream to parallel and synchronizing using FIFO.

Developed RTL Module for Parsing information from Stream and PSI Table Information abstraction.

Developed Micro-architecture for design and made its interface with ARM processor for transferring information to other sub modules and also for performing some mathematical operations.

Language: Verilog, VHDL.

Title: Ethernet TEMAC-UDP/IP Stack Implementation for real time Video Broadcasting (VoIP) System.

Role: Team Member

Details: This project was a part of Broadcasting Encoder. Multiplexed Encoded stream was forwarded on Ethernet using UDP/IP stacks (VoIP).Process involved in project was converting composite Video data into DVB format, then multiplexing different streams and these multiplexed steam was forwarded to UDP/IP stack model after PAT parsing, PCR correction.

Responsibilities:

Involved in creation of Design specification & Functional specification for project.

Involved in Development of Micro architecture design & ARM based SoC system design.

Developed RTL for LLC, MAC, and Network layer for Ethernet.

Developed RTL Modules for IP Resolution, Multicast, and Unicast Transmission.

Developed RTL Module for Multiplexing different stream from different sources using PCR resolution and PTS, DTS stamping in detail.

Developed test benches for verifying functionality of design in Verilog.

Language: Verilog, VHDL.

Title: Implementation of ‘SHA-1 HASH Algorithm’ up to 160bit data encryption.

Role: Team Member

Details: SHA-1 is Encryption algorithm that provides data security. Design was developed on client demand for encrypting for confidential product. Design was implemented in VHDL.

Responsibilities:

Involved in client requirement analysis.

Documentation on SHA-1 related pre-published papers.

Designed RTL Modules for Encryption using Hash-1(SHA1).

Developed test bench for simulation.

Developed Synthesis design files for developing next level of validation and verification.

Language: VHDL.

Title: Implementation of ‘AES Rijendael Algorithm’ for digital signatory device.

Role: Team Member

Details: Algorithm is designed using VHDL. Used for digital data security likes in digital signatory or other

Secure access based product.

Responsibilities:

Involved in direct client requirement understanding and developing plan for requirement of project with team.

Developed conceptual Flow graph and algorithm for generic design of AES.

Developed Functional Blocks for Encryption Methodologies like row shift, column mixing.

Developed architecture for polynomial multiplication.

Involved in developing different Modules for Cipher multiplication, substitution Matrix.

Decryption also performed for verification of design.

Developed Verilog test benches for design.

Developed different scenario for testing of design.

Decryption methodology developed for authentication of valid user identification.

Developed Different Blocks for Decryption and Encryption for AES Based Encryption System.

Language: VHDL.

Title: Implementation of ‘AMBA AHB Protocol’ for Master/Slave interfaces to Access Memory.

Role: Team Member

Details: Protocol is implemented for multi master and multi slave communication using arbiter and decoder. Max 16 Master and Slaves can access the bus depending priority level decided in Arbiter. Implemented for burst transfer between BRAM, DMA & Processor.

Responsibilities:

Detailed study of documents related to AMBA-AHB developed by ARM.

Detailed study of different hardware architectures to develop master control.

Thorough study of Micro architecture design in VHDL Verilog.

Study on synthesis, simulation, debugging.

Studied and made comparison with other communication protocols like I2C.

First design developed for Single master and two slave communication.

After extension of project, involved modules in design were Arbiter, Address decoder, Central Multiplexer.

Involved in study of decoder design and also a part of decoder design.

Developed RTL design for Arbiter for priority resolution.

Developed RTL Code for Centralized Mux. And priority resolution and slave activation.

Language: Verilog, VHDL.

Title: Implementation of Street Light Controller for power consumption reduction in rural areas.

Role: Team Member

Details: Implemented to reduce power consumption in rural areas. This project was having two phases of development, one for Street light circuitry design and another one is for RTL module development. IR Tx-Rx are used for detection of passing vehicle on road. And LDR based circuitry also developed for day night detection and then signals from IR have been forwarded to analyze and making light on-off where it is required.

Responsibilities:

Project was divided in electronics development part and RTL Coding part.

Involved in design specification development for product.

Transmitter Receiver system is designed using IR based Diode.

Also involved in Electronics development for LDR circuit to on-off street light.

Involved in designing Interface between electronics and design.

Developed RTL Module for controller, input feedback from IR to switching on Street light.

Involved in LDR based automatic on-off system design.

RTL VHDL codes were developed for testing and designing of project.

Language: VHDL.

Title: Device based on Power Line Career Communication for Voice transmission.

Role: Team Lead

Details: Project was based on Power Line Communication Technology for voice transmission. It was developed for transmitting voice over power line in a building to avoid extra wiring in home.

Responsibilities:

Thorough study &Understanding of digital communication for sampling, encoding, modulation, zero detection.

Detailed document study and analysis from datasheets of IC used for FSK Modulation, FSK Demodulation.

Project was developed using XR-2206, XR-2211, Op-Amps, and 555Timers ICS.

FSK Modulation, Demodulation was used for transmitting voice on Power Line using Zero crossing detection.

Different circuits were designed for Zero detection, Sampling hold, ADC, DAC.

Involved in FSK Modulation, Demodulation, and Zero detection.

PERSONAL DETAILS:

Date of Birth : 10th Jan 1991.

Marital Status : Single.

Father’s Name : Vijay Varshney.

Native Place & Nationality : Aligarh (U.P.), Indian.

Date:

Location: Bangalore. (Rajeev Varshney)

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