Vipul Mittal

#**/**, *** *****, *** Cross, Near Email: acvhhu@r.postjobfree.com

Swaraj Supermarket, Cashier layout, Linkedin: https://in.linkedin.com/pub/vipul-mittal/45/503/636 BTM 1st stage,Bangalore - 560068 Mob: +91-946******* Objective:

Seeking a challenging and rewarding position in ASIC Design and Verification industry where I can utilize my skills and experience to achieve the organizational goals. Experience Summary:

2+ year experience in RTL Design and Verification using VHDL / Verilog / System Verilog.

Experience in writing test benches, automation scripts and regression Test Suite.

Experience with Verification of protocols IPs like UART, AXI4.

Experience with Simulation run of protocols IPs like PCIe and DDR3.

Experience in Linting, Formal Verification and UVM verification methodologies. Skills:

Operating Systems: RHEL 6/7, Windows 7/8.

Programming Languages: Perl, Shell (learning), C, C++ basics. HDL & HVL: VHDL, Verilog, System Verilog, UVM.

Tools Used:

Simulation: ModelSim, QuestaSim.

Synthesis: Precision Synthesis (basics).

& Code Quality: Questa Formal, CDC and HDL Designer (Linting). Education:

Professional Development Course in VLSI System Design Sandeepani School of Embedded and VLSI Design (2014) Bangalore, Karnataka.

Post graduate diploma in VLSI Design

Centre of Development of Advance Computing - ACTS (2012 - 2013) Pune, Maharashtra.

Bachelor of Technology in Electronics & Communication Engineering Gyan Vihar School of Engineering and Technology (2008 – 2012) Jaipur, Rajasthan.

Employment:

Sep 2014 – Till date Application Engineer (EDA)

CoreEL Technologies Pvt Ltd,

Bangalore.

Application engineers in CoreEL Technologies are responsible for Design and Verification of ASIC/FPGA targeted projects of Defense and Corporate. Responsibilities:

Developing complete verification environment for designs using System Verilog.

Running Linting and Formal checks on RTL codes.

Documentation of Complete Verification Process with Test Plan, Bug Reports etc.

Delivering trainings on HDVL’s and Verification Methodologies. Training Delivered:

System Verilog and Universal Verification Methodology training in ISRO, Ahmadabad.

Assertion based verification using PSL and SVA training in NAL, Bangalore.

Xilinx Corporate Training "Designing with VHDL". Projects:

HDCP(High-bandwidth Digital Content Protection) 2.0 receiver design Description: This project involves the design of HDCP Tx and Rx to connect devices through HDCP protected interface. The Audiovisual content, encrypted by HDCP interface, flows through the system between authorized devices.

Contributions:

Implementation of AES algorithm in Verilog.

lint Checks for Safety critical compliance.

Module verification Using System Verilog.

Documentation of Verification.

Team size - 3

DDR3 Simulation Model integration with MIG

Description: The design was aimed to be working with microblaze processor in EDK where data had to be stored in a DDR3 memory of 1GB capacity comes with Kintex-7 KC705 evaluation board. The design had a MIG controller to interface with a DDR3 memory. Contribution:

Integrated DDR3 Simulation model from Micron with FPGA design Simulation.

Developed the Top level test bench modules in System Verilog Environment.

Done the top-level verification and functional coverage.

Reported bugs and worked with the design team in fixing the bugs.

Implemented Round robin algorithm for shared resources. Team size - 3

UART Verification

Description: This Design has been developed by client and Only Verification assistance was part of my responsibility.

Contribution:

Test bench creation for random data TX to RX of UART and verified the result in the scoreboard.

Regression tests suite was created against the code and functional coverage model. Team size - 1

Education Projects:

AXI-4 Lite Interface Design and Verification using System verilog. Description: We the team of four has done RTL design, Verification plan, Environment, Assertion, Functional Coverage and Documentation. (All 5 Channels)

VGA display of Spectrum and shapes over 640x480pixel screen. Description: We the team of two has done RTL design, Implementation on FPGA, Documentation for report.

Personal Details:

Languages: Hindi & English.

Marital Status: Single.

Hobbies: Gadgets & Sports.

Permanent Address: 97/2, Pushkar Gunj, Beawar, Ajmer, Rajasthan - 305901.

References available on request

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