PARUL GANGWAR

E: acvf5l@r.postjobfree.com M: +91-987*******

Educational Qualifications

Relevant Work experience

Intern – ST Microelectronics Pvt. Ltd. (July 2015- Present) Memory Solutions, Technology & Design Platform, Greater Noida Responsibilities includes:

1. Enhancement & Improvisation of Methodology for Statistical Analysis and Memory Scrambling Views. (M.Tech Thesis Work)

2. Memory Characterization

3. Benchmarking of different Memory Compilers.

4. Benchmarking of Memory based Simulators.

Research Projects

M.Tech Projects

1. Design of 4-bit Ripple Carry Adder & Carry Look Ahead Adder Using FinFET Designed adder’s circuit using Multi-Gate FET's with Cadence tool. 2. Design of SD-Card Controller with ASIC

SD-Card Controller for ASIC implementation. Gate level simulation was performed to obtain results. The design is simulated in Cadence (NC-launch). The design was synthesized in Cadence RTL (RC) compiler and physical design is done using Cadence Encounter tool (RTL to GDS II) in TSMC 180nm CMOS. 3. Design of Self-Biased Amplifier

Proposed different configurations of common source self-bias amplifier which eliminates the need of an external power supply for biasing.

B.Tech Projects

1. Comparison of Power Dissipation and Delay of Two Stage and Three Stage Voltage Sense Amplifier (1 year)

Three stage voltage Sense Amplifier was proposed which has faster response and has less power dissipation as compare two stage.

Degree Specialization College/ University CGPA/% Year M.Tech VLSI Design VIT University, Vellore 9.03 2014-16 B.Tech

Electronics &

Communication

Uttar Pradesh Technical

University

72% 2010-14

12th HSC GRM Sr. Sec. School, Bareilly 82% 2009

10th SSC Delhi Public School, Bareilly 78% 2007

Skills

Programming Shell Scripting, Perl, TCL, Verilog HDL Software Spice based simulators- Ams (ELDO) / Custom-Sim, Star-RC, Virtuoso, Calibre, Assura, Quartus II (ALTERA), Modelsim Operating Systems Windows, Unix, Linux.

Publications

Published a paper on “Comparison Of Power Dissipation And Delay Of Two Stage And Three Stage Voltage Sense Amplifier” in International Journal of Research in Engineering & Advanced Technology (IJREAT) Volume 2, Issue 2, Apr-May, 2014. http://www.ijreat.org/Papers%202014/Issue8/IJREATV2I2008.pdf Achievements

Presented on “Comprehensive Statistical Analysis of Full Memory IP for Better Quality Assurance” at ST-Synopsys Technology day held at STMicroelectronics, Greater Noida on 20th Jan’16.

Presented a paper on “Design of Self Biased Amplifier” in 10th International conference on Science, Engineering and Technology (SET), organized by VIT University in 2015.

Presented a poster on “Design of 4-bit Ripple Carry Adder & Carry Look Ahead Adder Using FinFET” in 9th International conference on Science, Engineering and Technology (SET), organized by VIT University in 2014.

2014 GATE qualified.

Held a position of Secretary of technical committee at SRMS College of engineering & technology.

Awarded and participated in National Level Olympiads and extracurricular activities at school level.

Extra-Curricular

Awarded and participated in sports and events related to art & craft.

Trekking and adventurous activities.

Listening to Music.

References

1. Mrs. Radhika Gupta 2. Mr. Sachin Gulyani

Senior Design Engineer, Manager Memory Solution

CAD Tools & Flows, Technology and Design Platform

STMicroelectronics Pvt. Ltd., Greater Noida STMicroelectronics Pvt. Ltd., Greater Noida acvf5l@r.postjobfree.com acvf5l@r.postjobfree.com

+91-991*******

Declaration: I certify that the information furnished above is factually correct. PARUL GANGWAR

(Signature)