PRAKRUTHI TG

974-***-****

acuzna@r.postjobfree.com

CAREER OBJECTIVE

Looking for a challenging career which demands the best of my professional ability in terms of technical and analytical skills, and helps me in broadening and enhancing my skills and knowledge.

EDUCATION PROFILE

Course

Institution

Board

Year of passing

Percentage of marks

M.Tech(Vlsi design &Embedded system)

UTL Technologies Ltd. Bangalore.

VTU Belgum

2015

64.33%

B.E(Electronics and Communication)

Malnad College of Engineering. Hassan

VTU Belgum

2013

8.09/10(CGPA)

73.34%

P.U.C(PCMC)

St. Philomena’s P.U.College

Hassan

P.U. Board, Karnataka

2009

73.16%

SSLC

Sri Vasavi Vidya Samasthe. Holenarsipur.Hassan

Karnataka Secondary Education Board

2007

87.52%

TECHNICAL PROFILE

Electronics and Communication,VLSI Design, Analog Design, Mixed mode signals, Layout design and Area minimization, Embedded system, RTOS, Product, and Application.

RTL coding, CMOS circuit design, simulation and synthesis.

Project experience in Analog Design using Cadence in Linux (RedHat) .Circuit design in Cadence Virtuoso® Schematic Editor L Editing, Simulation in Virtuoso® Analog Design Environment L Editing. RC Extraction.DRC and LVS.

CMOS, RF signals, S/H design.

Assembly Languages like 8086, 8051 skills.

Programming in C and C++ languages, HDL and Verilog languages.

Strong analytical, problem solving skills.

EDA Tools: Cadence Virtuoso® Schematic Editor L Editing, Virtuoso® Analog Design Environment L Editing. Virtuoso® Assura RC, Virtuoso® Assura DRC.

Programming Languages: C++/OOPs, VHDL, Verilog and System verilog, Assembly level programming (8085, 8086), 8051 Microcontroller.

ACADEMIC PROJECTS

Master’s Thesis:”Design and Implementation of Error Reduction Technique in Sample and Hold Circuit”. Under the guidance of Dr. Siva Yellampalli, The design is implemented in Cadence design environment.

This project is about implementation of error reduction techniques in sample and hold circuit(S/H) and comparison between various S/H architectures. The different architectures considered for this work are opamp based S/H,bootstrapped S/H and fully differential S/H.S/H suffers from multiple errors such as droop, charge injection, acquisition error, aperture jitter, etc. When a switch in the S/H turns on, the capacitor starts charging and discharges when it turns off, due to this action the sample output signal may suffers from attenuation. This project presents designing and optimization of differential S/H with error free in hold mode and less power dissipation. Fully differential S/H circuit is implemented with 100MHz sampling frequency, 10MHz of sinusoidal input frequency with the signal level of 0 to 1V.Fully differential S/H power consumed was 3mW.Aperture delay time was 12.38758psec and Droop rate was 6.04569mV/nsec, Settling time was 42.567psec and Hold step was 427.618pV which is comparatively better than opamp based S/H and bootstrapped S/H. The proposed architectures are designed and implemented in 0.18um CMOS Technology.

Project-“Design and Implementation of 1X4 router” in Verilog HDL.

Project-“Eco-friendly Traffic System By Using Solar Power And Reducing CO2 Emission With Fuel Saving Concept”

Project-“DMA Controller” under the guidance of UTL faculty.

Workshop on Embedded System conducted by IEEE

Workshop on “Optical splicing and optical measurement” conducted by Mr. C. Sanjay Kumar SDE, BSNL, Hassan.

CONFERENCE AND TECHNICAL PAPER

Paper entitled “Design and Implementation of Sample and Hold Circuit in 180nm CMOS Technology” selected for the IEEE Conference ICACCI-2015, Kochi, August, 2015.

PERSONAL DETAILS

Name : PRAKRUTHI T.G

Sex : Female

Date of Birth : 14-4-1992

Father’s Name : T.J. Gopalakrishna

Mother’s Name : Kumari

Marital status : Unmarried

Nationality : Indian

Languages Spoken, Read, Write : English, Kannada, Hindi

Address : PRAKRUTHI T.G

D/O T.J GOPALAKRISHNA

Sri Rameshwara Nilaya,Kikkeramma temple street

Fort, Holenarsipur, Hassan,

Pin code: 573211.

Email : acuzna@r.postjobfree.com

Phone : 974-***-****

I hereby declare that all the above particulars are true to the best of my knowledge.

PRAKRUTHI TG

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