BURRA HARIKRISHNA

Email:acuzh3@r.postjobfree.com Seven hills P G,

Mobile No.:+91-888******* NGR complex,

Arekere Main Road,

Bhannerghatta Road,

Bangalore, Karnataka.

SUMMARY

One year experience as an Intern at Maven Silicon Softech Pvt. Ltd.

Proficient with hands on experience in Digital Design with Verilog, Development of Verification Environment & Constraint Random Test Generation in UVM.

Strong Knowledge on Digital Electronics.

OBJECTIVE

To secure a job in core industry with a well established organization with a stable environment where I can maximize my technical skills and contribute positively towards the company’s growth.

EDUCATIONAL QUALIFICATION

Bachelor of Technology – Electronics & Communication Engineering

Pathfinder Engineering College, JNTU Hyderbad. April, 2014 – 72.2%

Board of Intermediate Education

Nagarjuna Co-operative Junior College, Hanamkonda. March, 2010 – 88.8%

Board of Secondary Education

Priyadharshini High School, Uppugal. March, 2008 – 82.8%

TECHNICAL SKILLS

HDL & HVL : Verilog HDL, System Verilog.

Verification Methodology : Universal Verification Methodology(UVM).

ASIC Design tools : Xilinx ISE, Questa Sim, Modelsim.

Platforms : Working knowledge of Windows, LINUX.

ACTIVITIES

Attended a two days of workshop on ROBOTICS at VRCE college, certified by

IIT - GOWHATI.

Participated in RINIA-2013 in our college.

PROJECTS

Projects done on

AHB – APB Bridge verification

Environment: UVM Methodology.

Project description : The AHB to APB bridge comprises a AHB slave, APB master, which is used to control generation of the APB and AHB output signals, and the address decoding logic which is used to Generate the APB peripheral select lines.

SPI Core Verification

Environment: UVM Methodology.

Project Description: In this project we have verified the serial communication between

two SPI cores based on the control signals of wishbone interface.

Physical Coding sublayer design

Environment: Verilog HDL.

Project description : In this project to develop the verilog code for Physical Coding Sublayer (PCS) which can be use for data transmission between two hosts at the same data rate.

Router 1X3 Design and Verification

Environment: Verilog HDL.

Project Description: The main aim of the project is to take the packet from source and send the packet to the correct destination depending on the address.

Verified the RTL using Verilog and UVM test benches.

Trace Buffer Observation Via Selective Data Capture Using 2-D Compaction Technique For Post Silicon Debug

Role: Team leader.

Environment: Verilog HDL.

Project Description: The main aim of this project is to manufacture a fault free IC fabrication using a technique called 2-d compaction and selective data capture method.

STRENGTHS

Ability to work in Team.

Positive Attitude and self confidence.

Good communication skills.

Adaptive to unfavorable situations.

PERSONAL INFORMATION

Date of Birth : 11-07-1993.

Languages : English & Telugu

Permanent Address : H.No : 4-77/2,

Village : Uppugal,

Mondal : Zaffergadh,

District : Warangal, Telangana State.

I hereby declare that the information mentioned above is true.

Place :

Date : B.HARIKRISHNA

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