Gaurav G. Bhatia

Electronics and Computer Engineer

832-***-**** • acuzet@r.postjobfree.com • Houston, TX • www.linkedin.com/in/gauravbhatiaatuofh OBJECTIVE:

Seeking an entry level full time position in Electrical & Computer Engineering Industry EDUCATION:

Master of Science in Electrical Engineering GPA 3.3/ 4.00 May 2016 University of Houston in Cullen College of Engineering, Houston- TX Courses: VLSI Design, Advance Digital Design, Advance Computer Architecture, Advance Topics in Computer Architecture, Robotics in Healthcare, Principle of Internetworking Bachelor of Engineering in Electronics & Communication GPA 3.75/ 4.00 June 2013 Visvesvaraya Technological University, Bangalore, India TECHNICAL SKILLS:

Programming Languages : C, C++, JAVA, Perl, Python, MATLAB

Hardware Description Languages: Verilog, VHDL, System Verilog, Embedded C, Assembly Languages

Software Packages : Model Sim, Quartus, LTspice, Pspice, Hspice, Spectre, Multisim, CALP, Keil Vision, Lab VIEW, Cadence Virtuoso, Xilinx ISE, MATLAB, Simulink

Platforms : Windows, Mac, Linux

Others : Microsoft Office, Adobe Photoshop, Advance MS Excel skills, Wireshark WORK EXPERIENCE:

Lecturer Aug. 2013 - June 2014

Bhagwan Mahavir College of Engineering and Technology, Surat, India

Tutored Digital Logic design and Advance Electronics Design curriculum to 3rd and 4th semester classes comprising of over 60 student which included 4 hrs. of face to face lecture and 16 hrs. of lab work

Mentored a team of 4 students with their research work on audio embedding techniques by using image processing techniques in MATLAB

Organized and managed Advanced Electronics lab for 4th semester students, as chief lab instructor ACADEMIC PROJECTS:

MIPS Pipeline Simulator, Houston, TX Jan. 2016 – May 2016

Simulated 7-bit MIPS pipeline processor using JAVA language for timing analysis

Implemented the simulation for 5 type of instructions to display the sequence operation of instructions Digital Timer, Houston, TX Aug. 2015 – Dec. 2015

Designed Verilog system of 4 digit display stopwatch using Modelsim and Quartus II

Wrote test bench in Verilog HDL code which verified the working of all timer modules

Synthesized SOC design and implemented on Altera Cyclone V DE-2 FPGA board Password Protection System, Houston, TX Jan. 2015 – May 2015

Designed a SOC synthesizable RTL code for data protection of system

Designed troubleshoot and verified Verilog HDL codes using Modelsim and Quartus II software

Interfaced and implemented the system on Altera DE-2 FPGA board Embedded System of a Pediatric Exoskeleton for lower limb rehabilitation, Houston, TX Aug. 2014 – Dec. 2014

Coded 32 bit Atmel 644PA microcontroller using C language to controls the actuators and LCD panel to display messages and alerts

Designed and tested the circuit for its functionality in Cadence and simulated in MATLAB

Developed an efficient and economical power supply for the system 5-Bit Ripple Carry Adder, Houston, TX Aug. 2014 – Dec. 2014

Designed a 5 bit Ripple Carry Adder CMOS VLSI layout

Did routing and placing using Cadence for optimal condition and power efficiency

Run LTspice simulation to measure the parameters of all units, such as propagation delay, rise time and fall time AWARDS & ACTIVITIES:

Won 3rd prize for paper presentation on ‘Surface Computing’ at the National Inter College Technical Paper Presentation Symposium, held at KSIT Bangalore