Srinivas Pusarla
E-mail: acuz86@r.postjobfree.com
Mobile: +91-949*******
CAREER OBJECTIVE :
To work in VLSI Domain where performance is rewarded with new responsibilities with knowledgeable environment and to grow along with the organization as a core member of the same.
ACADEMIC QUALIFICATIONS:
ÿ B.Tech in Electronics and Communication Engineering from Sri Chaitanya Engineering College affiliated to JNTUK with an aggregate of 68.3% in 2014. ÿ Intermediate (MPC) from Sri Chaitanya College affiliated to Board of Intermediate Education, Andhra Pradesh with an aggregate of 88.8% in 2010. ÿ 10th from Star Public School affiliated to Board of Secondary Education with an aggregate of 81.0% in 2008.
INDUSTRIAL TRAINING:
Trained in VLSI-Physical Designing from Institute of Silicon Systems Pvt. Ltd., Hyderabad from August, 2015 to January, 2016 using Cadence Tools. Key Skills:
C, TCL, Verilog, VHDL, ASIC, Physical Design, Floor Planning, Power Planning, CTS, DRC, STA, LVS.
Cadence Tools :
1. SOC Encounter - for Place and Route
2. ETS - for Static Timing Analysis
3. RTL Compiler - for Logic Synthesis
4. Virtuoso - for Standard cell layout
5. ASSURA - for LVS and DRC verfications
PROJECTS :
PHYSICAL DESIGN :
PROJECT 1 : Block 4
Gate count : 300K
Cell count / macros : 83026 / 4
No.of clocks : 17
Frequency : 200Mhz
Metal layer : 6
Technology node : 90nm
Role : Perform audit checks, Floorplan, Power plan, Placement, Trailroute & Congestion analysis, CTS, Detail Routing and Timing closure
Srinivas Pusarla
E-mail: acuz86@r.postjobfree.com
Mobile: +91-949*******
PROJECT 2 : Block 3
Gate count : 100K
Cell count / macros : 45460 / 5
No.of clocks : 6
Frequency : 230Mhz
Metal layer : 6
Technology node : 45nm
Role : Perform audit checks, Floorplan, Power plan, Placement, Trailroute & Congestion analysis, CTS, Detail Routing and Timing closure
PROJECT 3 : Block 2
Gate count : 138665
Cell count / macros : 23558 / 12
No.of clocks : 4
Frequency : 150Mhz
Metal layer : 5
Technology node : 130nm
Role : Perform audit checks, Floorplan, Power plan, Placement, Trailroute & Congestion analysis, CTS, Detail Routing and Timing closure
PROJECT 4 : Block 1
Gate count : 7701
Cell count / macros : 2477 / 0
No.of clocks : 3
Frequency : 333.33Mhz
Metal layer : 5
Technology node : 180nm
Role : Perform audit checks, Floorplan, Power plan, Placement, Trailroute & Congestion analysis, CTS, Detail Routing and Timing closure
LOGIC SYNTHESIS:
PROJECT 1 : Design 1
Objectives : Zero Wire Load and Force Wire Load Model Synthesis meeting ATP Constraints
Tools : RC Compiler
Gate count / area : 270 / 560µm
No. of Clocks : 2
Frequency : 200Mhz
Technology : Global Foundries 65nm
Role : Writing SDC, TCL Scripts, Extracting timings, Optimizing ATP
Srinivas Pusarla
E-mail: acuz86@r.postjobfree.com
Mobile: +91-949*******
PROJECT 2 : Design 2
Objectives : Running ZWLM Synthesis and achieving maximum possible frequency with different VT’s
Tools : RC Compiler
Gate count / area : 5488/7340µm (RVT) 6234/6555µm (HVT) 63540/6560µm (MVT)
No. of Clocks : 1
Frequency : 500Mhz
Technology : Global Foundries 65nm
Role : Writing SDC, TCL Scripts, Meeting ATP’s with zero slacks LAYOUT (STANDARD CELL DESIGNING)
PROJECT : Standard Cell Layout
Tools : Virtuoso Layout XL Editor, Assura Verification for DRC and LVS
Cells Designed : AND, OR, NAND, XOR, INVERTER, NOR Targeted Technology : TSMC 130nm
Role : Developing the Layout from Spice netlist and verifing DRC and LVS
Challenges : Routing using single metal layer by following metal’s pitch and Half DRC Rules
ACADEMIC PROJECT :
Title : ANTI-PERAL ROBOT
Description : This project is based on technologies of kiel software and using device called zigbee. This robot helps to detect the dangers such as fire, human, dangerous gases etc… and gives the sensed information to the computer wirelessly adopting zigbee module.
To control the direction of the robot we are using Xbee modules one as transmitter and other as receiver.
The transmitter is fixed to PC and the receiver is fixed to the robot on the other end. We send signals from PC through the Xbee (transmitter) to the receiver which is in built to the robot.
PERSONAL PROFILE:
Father’s Name : P. Satya Rao
Mother’s Name : P. Guna Satyavathi
Date of Birth : 10th July, 1993.
Languages Known : Telugu, English
Current Location : Hyderabad (Flexible to migrate)