Carrier Objective:
A challenging career in Analog Layout design which will allow me to contribute for the advancement of technology.
Education qualification:
ME(ES &VLSID) in MVSR Engineering College affiliated by Osmania University with an aggregate of 66.6% (till date) completed in the year 2016.
B.TECH(ECE) in Malla Reddy Institute of Technology affiliated by Jawaharlal Nehru Technological University, Hyderabad with an aggregate of 71.2% in the year 2014
Intermediate(MPC) from Board of Intermediate Education, Hyderabad with an aggregate of 83%. in the year 2010
SSC from Board of Secondary Education, Hyderabad with an aggregate of 78%. in the year 2008
Industrial training:
Got trained in VLSI Analog Layout Designing from Institute of Silicon Systems Pvt. Ltd., Hyderabad from 4th January, 2016 to 8th April, 2016 using cadence tool.
Cadence tool :
Technology used : TSMC 130nm and GPDK 45nm
Virtuoso Layout Editor : Designing layout
Assura and PVS : Physical verification
Digital Layout Projects:
Project 1: Standard cells layout designing
Tool : Virtuoso Layout Editor, Assura (DRC and LVS )
Cells design : Inverter, NAND, NOR, EXOR, AND, OR, DFF
Technology used : TSMC 130nm
Role : Designing layout from SPICE netlist and verifying the design DRC and
LVS clean
Challenge : For routing only metal 1 is to be used and maintaining half DRC rules.
Analog Layout Projects:
Tool : Virtuoso Layout Editor for floor planning and routing, PVS (DRC and LVS)
Technology used: GPDK 45nm
Project 2: Level Shifter
Description : Level shifter is used to convert one voltage into another voltage
Role : Designing layout from schematic and verifying the design DRC and LVS clean
Challenge : Separation of two different voltages by using Sxcut layer
Project 3: Op-Amp
Description : Op amp is a dc coupled high gain voltage amplifier
Role : Designing layout from schematic and verifying the design DRC and LVS clean
Challenge : Matching devices and shielding critical nets
Project 4: Bandgap Reference
Description : A bandgap voltage reference is a temperature independent voltage reference
circuit which produces a fixed voltage regardless of power supply variations,
temperature changes
Role : Designing layout from schematic and verifying the design DRC and LVS clean
Challenge : Matching for BJT's and resistors and shielding differential inputs
Project 5: DAC
Description : DAC is used to convert digital signal to analog signal
Role : Designing layout from schematic and verifying the design DRC and LVS clean
Challenge : Resistor matching, maintaining EM, Maintaining metal orientation and drawing
the layout in optimized way.
Project 6: PLL
Description : Phase-locked loop can track an input frequency, or it can generate a frequency
which is a multiple of the input frequency
Role : Designing layout from schematic and verifying the design DRC and LVS clean
Challenge : Maintaining EM, getting output with less parasitics and shielding the outputs
and drawing the layout in optimized way.
Skill Gained :
Floor Planning and Power Routing
Verifying the design DRC and LVS
Matching devices with respect to PVT
Formation of Parameterized Cells (P-Cells)
Shielding the nets
ESD Effect
Antenna Effect
IR and EM Effects
WPE Effect
STI and LOD Effect
Latch-up
Academic projects:
Project title : PREPAID ENERGY METER WITH RECHARGING UNIT USING SMART CARD
Description : The main objective of the project is to the reduce problem associated with billing of consumer living in isolated area and reduces deployment of manpower for taking meter readings by recharging a smart card in units and use accordingly.
Personal Profile:
Father’s name : Nallappa K
Mother’s name : Saraswathi K
Languages known : English, Telugu
Current Location : Hyderabad (flexible to migrate)