KEYUR DESAI

(Mas ters i n El ec t roni cs, USA)

E-Ma i l : keyur . desa i@l i ve . com

Phone :+91-852*******

VLSI Design Engineer

Scaling heights of success, targeting mid-level assignments in ASIC/FPGA Designing & Verification with a reputed organization, prefereably in IT / Hardware industry Preferred Location: Bangalore / Hyderabad / Ahmedabad / Delhi-NCR PROF I L E SUMMARY

• Versatile, high-energy professional with an experience of 5 years

• 2 years of experience in Designing & Verification, Project Management, and Debugging & Troubleshooting

• 3 years of experience in Commisioning & performing Acceptance Test for Nokia BTS, Nokia Microwave and NEC Microwave

• Presently associated with Tevatron Technologies Pvt. Ltd., Noida as VLSI Design Engineer

• Proficient in Verilog and VHDL modeling, logic synthesis and verification using System Verilog and UVM

• Displayed excellence in BFM (Bus Functional Module) of complete AHB architecture and different test cases to check multi-slave operations and data transfer through AHB Slave

• Proven skills in debugging and solving highly technical issues

• Possess sound knowledge of ASIC design flow which includes designing, verification, prototyping & time analysis and test development

• A keen communicator with honed interpersonal, problem solving and analytical skills ORGAN I SAT I ONAL EXPER I ENC E

Jan’15 - Present - Tevatron Technologies Pvt. Ltd., Noida as VLSI Design Engineer

(Tevatron Technologies (A registered private limited company under Ministry of Corporate Affairs, Govt. of India) is a Design and Product Company focused on VLSI Design, FPGA Based Design & Embedded Systems and nurturing the ecosystem for the same)

Growth Path

Jan’15 – Jun’15: Intern

Jun’15 – Present: VLSI Design Engineer

Role:

• Managing the hardware testing, hardware design like architecture drawings, system / marshalling cabinet as well as entire design drawings and layout drawings

• Working on AHB protocol; writing verification environment for AHB Master and Slave in UVM

• Verifying AMBA AHB Bus Master & Slave through UVM and Wishbone Interface Memory Controller IP Core

• Coordinating for the project activities and preparing specifications with the clients to ensure drawings are per the specifications of clients

• Administering the derivation and development of design solutions with customer to meet functional requirements within the specific constraints

• Passing Constrained Random Stimulus for Functional Coverage and Data Coverage

• Redressing the errors in one or multiple programs as desired and entering new data and controlling the program execution by the scheduler

Highlights:

Wrote:

o Verification Environment to test Wishbone Interface Memory Controller IP in SystemVerilog o Different test cases to verify the functionality of Memory Controller with Multi-master

Passed Random Constrained Random Stimulus for Functional Coverage and Data Coverage June’04 - Aug’07 - Arya Communication & Electronics Services Pvt. Ltd., Ahmedabad as Project Coordinator

(Arya Communications & Electronics Services Private Limited has been at the fore front of providing top of the line communication solutions to its diverse customer segments. It offers end-to-end cutting edge solutions in the field of wired and wireless communications, security and surveillance, professional engineering services and emerging technology platforms. An ISO 9001:2008 certified company; Aryacom has been consistently providing reliable and customized turnkey products, solutions and services)

Growth Path

June’04 – Jan’06: Engineer

Jan’06– Aug’07: Project Coordinator

Highlights

• Selected as a Lead Engineer for Overseas Project at Maldives for Commissioning & Integration of NEC MW Radios and Motorola BTS for Wataniya Telecom

• Commissioned, integrated and performed Acceptance Test (AT) of Nokia BTS and NEC Microwave Radios

• Led team of 8 people to install and commission NOKIA BTS

• Successfully met all the project target deadlines

• Provided post commissioning support to stabilize the operations

• Managed performance tuning and optimization of the equipment that improved completion of task in 2 days instead of planned 3 days

I NTERNSH I P S

Title: Interfacing of PS2 Keyboard & LCD via FPGA

Description: Designed & implemented a module on FPGA connecting PS2 Keyboard & LCD Screen. Implemented functionality of “Enter” and “Backspace” key code on FPGA Outcomes: Alphabet or number pressed on PS2 keyboard was displayed on LCD screen. Title: Interfacing of Desktop Monitor to the FPGA via VGA Description: Designed and implemented modules to interface FPGA with PS2 keyboard &desktop monitor via VGA adaptor

Outcomes: Image stored on FPGA ROM WAS displayed on desktop monitor. Based on the arrow keys pressed, image was rotated right, left, up & down.

Title: Interfacing of Micron 512 MB DDR RAM with FPGA Description: Designed & implemented modules interfacing 512MB DDR RAM & PS2 key board with FPGA Outcomes: Data was written to DDR RAM from the key board and the same was verified by displaying the data on LCD screen.

PRO J ECT S

FPGA Based Projects Aug’13 – Mar’14

Title: UART Controlled Rotating LED Banner

Description: Designed and implemented receiver and transmitter module of UART and rotating LED banner in Verilog and implemented on FPGA

Outcomes: 10 digit stored on memory was displayed on 7 segment LED. The LED banner rotated, paused / reversed the direction of rotation based on ASCII code received. Title: Microblaze Softcore Processor

Description: Implemented Microblaze Softcore Processor using Xilinx EDK onto the Digilent Nexys2 (Xilinx Spartan 3e) FPGA. Wrote a code in C, to turn LED's on and off, based on the status of the DIP switches.

Title: Real Time Clock

Description: Designed and implemented stopwatch and clock on FPGA Outcomes: FPGA was displayed the clock on 7 segments LED and stopwatch counter. ACADEMI C DETA I L S

• M.S. (Electronics) from California State University Northridge, USA in 2012

• B.E. (Electronics & Telecommunication) from Dr. Baba Saheb Ambedkar Marathwada University, Aurangabad in 2004 C ERT I F I CAT I ON

• Nokia Certification as a Licensed Engineer for BTS Commissioning ACADEMI C PRO J ECT S

During Masters

Title: Design Synthesizable Asynchronous FIFO by using 90nm Library Tools Used: Cadence, Synopsys DC –Compiler, Prime Time, IC -Compiler Description: Designed asynchronous FIFO using Verilog for 8, 16 and 32 bit of data. Verified the design by using MBIST. Automated the test bench that was generated in Cadence by using NC Verilog. Synthesized the design by using top – down and bottom-up methodology by using Synopsys’s DC Compiler. Inserted DFT in the design for testability. Performed STA by using Prime Time to identify and remove violations.

Title: Design RISC CPU

Tools Used: Cadence, Synopsys DC – Compiler, Prime Time, IC –Compiler Description: Designed RISC CPU by using Verilog for 8 bit data. Verified design in Cadence by using NC Verilog. Synthesized the design with DC compiler in 90nm library by using bottom up method. Performed STA to identify and remove all violations.

Title: Design MIPS Multicycle CPU

Tools Used: Xilinx, ModelSim

Description: Designed MIPS Multicycle CPU for 32 bit data in VHDL by using Xilinx Design tools. Performed LW

(Load Word), SW (Store Word), ADD, SUB, AND, OR operations using multicycle CPU. Verified the design by using ModelSim.

IT SK I LL S

Programming: Verilog, VHDL, SystemVerilog, C++

Verification

Methodology: UVM

Operating Systems: UNIX (Solaris), Ubuntu, Windows Tools: Cadence, NC Verilog, QuestaSim, Xilinx ISE, Modelsim, Synopsys-DC compiler, Synopsys-Primetime, Altera Quartus

FPGA: Digilent Nexys2 with Xilinx Spartan 3e FPGA, Spartan 3E Starter Board with Xilinx Spartan 3E FPGA

(500K Gates)

PERSONAL DETA I L S

Date of Birth: 5th August

Languages Known: English, Hindi & Gujarati

Address: B-306 Urmil Co-Op Housing Society, Charwadda Road, Vapi 396 191

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