S SUDHEER SAGAR

Vellore Institute of Technology University Phone: +91-994*******

Chennai, Tamil Nadu – 600048 Email: acuulb@r.postjobfree.com OBJECTIVE

To secure a challenging position that allows me to perfect my skills in the field of Very Large Scale Integration (VLSI) design. I want to work with a progressive organization, where I can utilize my knowledge and skills for the mutual benefit of the organization and myself. ACADEMIC QUALIFICATIONS

TECHNICAL SKILLS

Design Skills

Operating Systems

EDA Tools

Analog design, Layout, Verilog, ASIC, Basics in PERL, TCL DOS, Windows XP/7/8, Linux

CADENCE® (Virtuoso, NC Launch, RC, Encounter)

XILINX® ISE, Model Sim

PROJECTS

Design of DC-DC Boost Converter (Sep 2015 – April 2016)

Design of voltage boost converter with 5V input and 25V output

Power stage with continuous conduction mode

Feedback loop with current mode control

Design of CMOS flash ADC with reduced number of comparators (Dec 2014 – April 2015)

An efficient multiplexing technique is used to reduce the number of comparators

Design of high speed comparator with efficient MUX designs, in CADENCE® virtuoso -64

Layout is designed in CADENCE® Layout –XL, verified by CADENCE® Assura Low-power Low-offset Dynamic Latch Comparator (July 2014 – Nov 2014)

Modified Conventional Comparator Circuit is to achieve low power and speed of operation even in small supply voltages

The circuit is designed in 0.18μm CMOS technology

The tool used to design is CADENCE® Virtuoso

Optimized Implementation of FFT Processor for OFDM Systems (Nov 2012 – Feb 2013)

Implementation of the 8point FFT processor with radix-2 algorithm for R2MDC architecture

Coding is done using the VHDL and simulated using the XILINX® ISE 10.1 simulator YEAR COURSE INSTITUTION PERCENTAGE/CGPA

2016 M.Tech (VLSI) Vellore Institute of Technology University, Chennai 9.05 2013 B.Tech (ECE) Sri Sivani College of Engineering, Srikakulam 69.59 2009 Intermediate Sri Chaitanya Junior College, Vishakapatnam 85.7 2007 High School Venus Public School, Rajam 83.5

SUMMER INTERNSHIP

Broadcasting in All India Radio (A.I.R) (May 2012 – June 2012)

Have been familiarized with the familiarization of studio equipment

Have been trained on How the Broadcasting is done by using different equipment OTHER PROJECTS

Advanced Parking system and implemented on FPGA kit

Radio frequency based Sound system

Jugaad Projector

ACHIEVEMENTS

Received GATE stipend of Rs.4000 per month at VIT University for good score in GATE 2014.

Participated in the workshop on CYBORG-The Robotics Workshop conducted by KYRION ROBOTICS CLUB.

Participated in the ENTREPRENEURSHIP AWARENESS CAMP organized by Centre for Entrepreneurship Development (CED), Hyderabad.

Participated in National Service Scheme (NSS) and won accolades from College.

Presented a paper on WITRICITY in GMR INSTITUTE OF TECHNOLOGY, Rajam. HOBBIES

Browse Internet, sketching, reading novels and magazines PERSONAL DETAILS

Father’s Name

Gender

Nationality

Date of Birth

Languages Spoken

S Satyanarayana

Male

Indian

25th August, 1992

English, Hindi and Telugu

Contact this candidate