RESUME

SRIKANTH M

Mobile no: +91-810*******

Email Id:acut1w@r.postjobfree.com

Objective:

To establish myself as a professional with a challenging careers, prospects are unlimited and has ample scope of learning and keep the abreast with latest technological trend in the industry and to work to my best of abilities and be part of winning team.

Profile Summary:

09 months of experience as VLSI RTL Developer, working at Data Point Info Solutions Pvt. Ltd, Hyderabad from August 2015 to till date...

Programming expertise in Verilog HDL, VHDL, C, and Java.

Good communication, written and interpersonal skills.

Technologies:

IDE: Xilinx ISE 14.5, Cadence Virtuoso tool, Cadence Incisive Simulator, Cadence Encounter tool.

Operating System: Win XP, Windows-7, Red Hat Linux.

Web Technologies: HTML, XML, JavaScript.

Programming Languages: C, Java.

Hardware Languages: VHDL, Verilog HDL.

Data Base: Oracle 10g.

Application: MS Office.

Strengths:

Good analytical and programming skills.

Quick learner and ability to grasp new technologies.

Journals published:

“Design And Implementation Of LTE For Low Power Operations” published in IJMETMR,YUVA ENGINEERS JOURNAL, Hyderabad in July 2015 issue(Volume 2, Issue7)

Academic Qualification:

Master of Technology (M.Tech) (2015) from JNTU Hyderabad with 80% aggregate.

Bachelor of Technology (B. Tech) from JNTU Anantapur (2009) with 64% aggregate.

Intermediate (M.P.C) from Board of Intermediate Education (2005) with 61% aggregate.

S.S.C. from Board of Secondary Education (2003) with 73% aggregate.

Workshop Attended:

Two days hands on National Level workshop on “EDA Tools for Communication Engineers” conducted by DST, New Delhi organized by HITAM ECE Dept. in Hyderabad January 2015.

Three days hands on National Level workshop on “NI Graphical System Design” conducted by conducted by NI, USA organized by HITAM ECE Dept. in Hyderabad August 2014.

Academic Project:

Title : Design and Implementation of LTE for Low Power Operations.

Tools Used : Xilinx ISE, Verilog HDL.

Operating System : Windows XP SP3.

Duration : September 2014- August 2015.

Description: LTE is an emerging standard for high-speed wireless communications. Design and Implementation of Long Term Evolution (LTE) front end modules to synchronize time and frequency with the help of Fast Fourier Transform (FFT). The synchronizer proves to have an outstanding performance with less delay time with simple circuitry for all defined communication modes in LTE.

Achievements:

Got Best Student award from my college in Intermediate

Got Best Cadet award from NCC.

Personal Profile:

Full Name : M.SRIKANTH

Father’s name : Koteswara Rao M

Date of Birth : 01-06-1988

Gender : Male

Known languages : Telugu, English

Present Address : H.NO:4-55/2/G

Prasanthi Nagar Colony,

Quthbullapur,

Hyderabad-500055

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