SHINO JOSEPH

ROSEVILLA, ILLIKKUNNU, NETTUR P O, THALASSERY, 670105 996-***-**** acunv7@r.postjobfree.com

Objective

Recently graduated M-TECH in VLSI DESIGN seeking a job in the field of Analog IC design and analog layout design

Technical Skills

Programming Languages : C and C++

Hardware Programming Languages : Verilog HDL (using Xilinx ISE Editor for FPGA, Cadence NC launch and Encounter digital implementation )

EDA Tools :Cadence Virtuoso, LT Spice

Scripting Languages: Perl and TCL

Operating Systems: Windows

Software Tools : Microsoft Office

Education

M-TECH VLSI DESIGN 2016 VIT UNIVERSITY CHENNAI CGPA-8.36

B-TECH ECE 2009 LBS COLLEGE OF ENGINEERING KASARAGOD 62.89%

PLUS TWO 2005 ST.JOSEPHS HSS THALASSERY 84%

SSLC 2003 ST.JOSEPHS HSS THALASSERY 88.83%

Course projects

UG PROJECT

IMPLEMENTATION OF DSO USING FPGA

Aim of the project is the implementation of fast and accurate DSO with less circuitry. It has utilized with the very promising FPGA technology with Xilinx. The technology can be applied in the developing oscilloscope that re easily transportable the need of computer system display can be replaced by the VGA display and integrating it with the device. The technology enables oscilloscopes to be produced at a much cheaper cost.

PG PROJECTS

MEMRISTOR based hybrid architecture of NVRAM

Aim of this project is to reduce the number of MOSFETs in the SRAM design as well as the total power. The Memristor is a device which has resistance with memory, when a potential is applied to this element its resistance changes and remains on that particular value even after the source is removed. Non-volatile property and high packing density in a crossbar array makes Memristor a magic device. The implementation of SRAM circuit with hybrid architecture of Memristor and MOS transistor was done. . The advantage of using Memristor is its non-volatile property. The low heat generation is an important characteristics. The Verilog A model of Memristor in nonlinear ion drift process is used for simulation. The Memristors which are connected inversely can hold the data as well as and can be retrieved on the application of reverse voltage. Pass transistors are used for data transmission and differential amplifier is used as sense amplifier. Since less number of MOSFTS are used in the RAM design reduces the total power dissipation. A 4*4 array of NVRAM had built in cadence® virtuoso and the working parameters are observed.

SCHMITT TRIGGER based SRAM

The bit cell architecture provides the better design solution for the conflict between read and write operation. Schmitt trigger feedback mechanism avoids the threshold voltage variation and hence protects the SRAM bit cell from process variations Several SRAM bit cell with different number transistors are available. For the low power application the supply voltage need to be reduced since the dynamic power consumption is more dependent on square of voltage. Analysis and comparison of differential sensing modified 10 transistor SRAM with Schmitt trigger based feedback mechanism with conventional 6 transistor SRAM bit cell is done. The bit cell architecture provides the better design solution for the conflict between read and write operation. Schmitt trigger feedback mechanism avoids the threshold voltage variation and hence protects the SRAM bit cell from process variations. The layout simulation of the two novel Schmitt trigger based SRAM and conventional 6-T SRAM is done in 180nm technology.

Implementation of high performance OTA for high frequency applications

The paper deals with the design and implementation of two types of operational transconductance amplifier. Current reused technique current mirror OTA for the gain enhancement and the body driven and the multi input stage with CMFB OTA are implemented using 180nm technology. The former achieve the gain of 64dB phase margin of 50 bandwidth of 92 MHz and latter design achieves the gain of 42dB with bandwidth of 250MHz and the power consumed by circuit with the CMFB is less than 0.8mW.

Additional information

Went for industrial in plant training for a week in ITI, Bengaluru

LANGUAGES

Fluent in reading, speaking and writing MALAYALAM.

Fluent in reading speaking and writing ENGLISH.

Passed IELTS with score 6.5

Fluent in reading and writing HINDI.

LINKEDIN URL

https://in.linkedin.com/in/shino-joseph-82461737

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge

Chennai Signature

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