HEMANTH KUMAR MOTAMARRI

Contact: +91-949******* Email:acukoj@r.postjobfree.com

ACADEMICS

**** *.**** (VLSI) JNTU Kakinada

75.00%

**** *.**** (ECE) PSCMR college of Engineering and technology 74.31 % 2010 Intermediate Sri Chaitanya Junior College, Vijayawada 94.50% 2008 SSC CheguVidyalayam 90.00%

ACHIEVEMENTS

Secured a rank in top 13% in Gate-2014 (ECE).

Secured 853rdrank in 10th NATIONAL IT APTITUDE TEST conducted by ORACLE (out of 80,000 applicants).

Achieved 1st prize in Inter State Mathematics Competiton Test - 2006 (District level).

Achieved 1st prize in Inter State Mathematics Competiton Test - 2005 (District level). TECHNICAL SKILLS

Knowledge on VLSI Fundamentals, ASIC Flow, Digital Design, Physical Design, Low power Techniques, STA. Hardware languages : Verilog, Basics of system verilog. Programming Languages : Basics in C.

Scripting languages : Basics in Tickle, Perl.

EDA Tools : Synopsys VCS, Design Compiler, IC compiler, DFT compiler. M.Tech(Main Project)

Built in generation of functional broad side tests using fixed hardware structure using verilog.

Designed, tested the faults in S27 circuit.Simulated using VCS.Test patterns were generated using LFSR of 12 bit size.

Hardware was based on application of primary i/p sequences to allow the circuit to produce reachable states.

Random primary i/p sequences were modeled to avoid repeated synchronization by a decoder b/w circuit and LFSR.

Two pattern tests were obtained by using pairs of consecutive time units of the primary input sequences.

Functional broad side tests required simple hardware and achieved high transition fault coverage for testable circuits.

Here S27 circuit accepts i/p of 4 bit length and 3 bit i/p to FF’s present. This is operated in functional mode. M.Tech(Mini Projects)

Design, simulation of USB 3.0 Super speed Physical Layer.

Physical Layer contains PCI Express and PIPE interface.

Data transferred serially either on 2.5 GT/s or 5.0 GT/s depending on mode rate,designed the speeds using verilog.

The design generates clock that runs on two different frequencies 125 MHz and 250MHz using verilog coding.

In this i captured the asynchronous data and lock the Rx clock with incoming Asynchronous serial data. Design and simulation of Elevator based Control system using verilog.

Elevator controls the entire operation of dual elevator system and is implemented for multi-storage building.

Control algorithm is written in verilog and simulated using Synopsys VCS tool.

Different sensors in it sense the position,status of obstruction of Elevator and the requests are read through FF’s.

If the door of any elevator is opened then timer signals from the elevator keep the controller informed of being busy.

In this design the internal requests are given priority than external requests.

Performed physical design using Synopsys IC tool. B.Tech

Orthogonal space-time block codes for MIMO OFDM chanels using MATLAB.

A class of Space-Time Block codes over Frequency Selective Ray leigh fading channel are proposed. Role : Design of Ray Leigh fading in AWGN channel.The signal fades due to fading coefficients. Here the Ray Leigh channel is designed in matlab by appropriate fading coefficients. This channel is suitable mainly in urban areas where there is no proper line of sight betweenTx and Rx. CAREER OBJECTIVE

To obtain a position in a people-oriented organization where I can maximize my experience in a challenging environment to achieve the corporate goals.

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