UMANG SHARMA

**** ******** **., ***. # ***, Los Angeles, CA 90007 • 323-***-**** • acukjq@r.postjobfree.com • LinkedIn EDUCATION

University of Southern California, Los Angeles May 2015 Master of Science, Electrical Engineering Coursework related GPA: 3.38/4.0 Relevant Coursework: Diagnosis and Design of Reliable Digital Systems, MOS VLSI Circuit Design, VLSI System Design, Computer Systems Organization, Computer Systems Architecture, Real Time Computer Systems University of Mumbai, India July 2013

Bachelor of Engineering, Electronics Engineering GPA: 71.5/100 TECHNICAL SKILLS

Programming Languages: Verilog, C, Perl, Python, VHDL

Tools: ModelSim, Cadence Virtuoso Layout Editor, NCSim, SoC Encounter, Synopsys Design Compiler, PrimeTime, Eclipse IDE, gcc

EXPERIENCE

Graduate Research Assistant - USC Ming Hsieh Department of Electrical Engineering Spring 2015 - Present

Researched under Prof. Mary Eshaghian-Wilner on the importance of Pervasive Computing in Nanomedicine.

Assisted in creating proposals for grants from PHS funded agencies such as National Institutes of Health (NIH). Grading Assistant - USC Ming Hsieh Department of Electrical Engineering Spring 2015

Assisted Prof. Monte Ung with the course EE554: Real Time Computer Systems. ACADEMIC PROJECTS

Design for Testing Fall 2014

(C programming, gcc)

Implemented ATPG and fault simulator algorithms for ISCAS ‘85 benchmark circuits.

Applied programming competency in C to implement preprocessor which provides collapsed fault list to ATPG (D-algorithm and PODEM). ATPG generates test vectors for corresponding faults.

Fault Simulation algorithms (Deductive Fault Simulation and Parallel Fault Simulation) verify correctness of ATPG. Tomasulo Out of Order (OoO) Processor Fall 2015

(VHDL, ModelSim)

Designed and implemented 32-bit out of order execution processor with MIPS ISA (Tomasulo Algorithm).

It has 32 Architecture Registers (ARF), 48 Physical Registers (PRF), 2-bit Branch Predictor Buffer (BPB), 4-location Return Address Stack (RAS), 8 Copy Free Check-pointing (CFC) buffers and 8-location Issue Queues.

Retirement-RAT (RRAT) and CFC buffers designed to enhance performance during rollback situations. ASIC Design of DDR2 Memory Controller Summer 2014

(Verilog, NCSim, Design Compiler, PrimeTime STA, Conformal LEC, SoC Encounter)

Designed DDR2 controller processing logic, with FIFO interface and initialization sequence.

Interfaced with Verilog model for Micron MT47H32M16 DDR2 SDRAM provided by Denali.

Implemented Scalar, Block and Atomic read/write transactions to and from 512MB DDR2 SDRAM. General Purpose Microprocessor Spring 2014

(Cadence Virtuoso Layout Editor, TSMC 180nm, Perl)

Designed schematic and layout of 64-bit microprocessor which supports arithmetic and burst operations.

Interfaced with 1Kb SRAM, having four 256-bit banks and 64-bit tree adder sized by implementing Logical Effort.

Verified execution results of instruction sequence through Perl script. FIFO Design Summer 2014

(Verilog, Design Compiler)

Designed and synthesized a single-clock domain circular FIFO (500 MHz clock).

Designed and synthesized a double-clock domain circular FIFO (20 MHz for read clock; 200 MHz for write clock). 5-Stage Pipeline Unit Fall 2013

(Verilog, ModelSim)

Implemented 5-stage pipeline unit supporting Forwarding Unit (FU) and Hazard Detection Unit (HDU).

Design supports 32-bit addition, subtraction and move operations.

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