LEEMA RACHEL MATHEW

+91-813*******

acujy0@r.postjobfree.com

CAREER OBJECTIVE

Aspire to work and grow in an organization that offers a challenging and responsible work atmosphere to use my acquired knowledge and its applications to accomplish individual goals while realizing organizational goal.

PROFILE

Graduate in M.Tech (VLSI Design and Embedded systems) from Sahyadri college of Engineering and Management, Mangalore. Able to work as own initiative as a part of a team and excellent inter personnel relations from all walks of life. Self-motivated, ability to work on multi-task jobs and meet the schedule deadlines. Good written and oral communication skills.

EDUCATIONAL QUALIFICATION

COURSE

UNIVERSITY

COLLEGE

YEAR

PERCENTAGE

M.Tech

Visvesvaraya Technological University Belgaum

Sahyadri College of Engineering and Management, Mangalore

2015

72

BE

Electronics & Communication

Visvesvaraya Technological University Belgaum

KVG College of Engineering,

Sullia

2013

70.61

PUC

Department Of

Pre-university Education Karnataka

St Agnes PU College

Mangalore

2009

70.33

SSLC

Karnataka Secondary Education Examination Board

Jnanodaya Bethany

High school

Nellyady

2007

86.40

SKILL SET- Test automation experience as a part of project in Qspiders.

MANUAL TESTING

As a part of Qspider undergone training in manual testing with a detailed knowledge of,

White box testing, its importance, and types of white box testing.

Detailed flow of black box testing.

Functional testing of each and every component in the application.

Integration testing, end to end testing in an environment similar to production environment (System Testing)

Globalisation testing like Internationalization testing (I18N) and localization testing (L10N) for various country standards.

Compatibility testing wherein application is tested in various platform for both mobile and pc application.

Having very good knowledge of SDLC and STLC.

Basic knowledge about scrum process in agail methodology.

ADDITIONAL SKILLS

Xilinx ISE, Questasim and Mentor Graphics.

Hardware Description Languages like Verilog and VHDL.

PROJECTS UNDERTAKEN

1. Mobmerry

Mobile application testing

Duration: 2 days

Mobmerry is an E-Commerce application where retailer sells their product. Here there is no home delivery option instead one has to put the selected item in wishlist so that it will be notified when near to that store or when product is on sale. It also provide option to buy the product by directly visiting the shop. This app is available in Android play store and IOS app store.

Roles and responsibilities

System study

Identified all possible scenarios and documented those scenarios.

Written tescases.

Performed integration, Smoke and functional testing.

Found 8 bugs.

Used Jeera tool for tracking the bug.

2. Browser Compatibility testing

Duration: 1 week

Compatibility testing was done on 3 jewellery application such as Bluestone.com, Caratlane.com and Craftvilla.com on different browsers. BlueStone is an online jewellery store that houses high quality jewellery and accessories with strikingly exquisite designs. CaratLane.com is one of India’s leading e-commerce company and one of the most visible online brands. Craftsvilla.com uses a marketplace model to capture the regional variations of India.

Os used: Windows 7 Ultimate

Browers: IE8, Chrome 47, Mozilla 43

Bugs found: 20

3. “Optimization and verification of Bus Interface Unit (BIU) of the in-house developed 32-bit RISC processor core to increase performance”.

To enhance the performance of the in-house processor by modifying the BIU so that the MIPS rating is improved and the processor core can be used for design of high speed embedded systems and also FPGA prototyping is done for the modified.

INDUSTRIAL TRAINING

ORGANISATION: ANURAG, DRDO, Hyderabad

DURATION : 5 Months

DESCRIPTION : Optimization and verification of Bus Interface Unit (BIU) of the in-house developed 32-bit RISC processor core to increase performance.

BIU is an important module in processor architecture which forms the backbone for all accesses of the processor with the external peripheral interfaces which can be either memory mapped or I/O mapped. The optimization, verification and FPGA prototyping of the existing BIU in the in-house developed processor core is done by analyzing and reducing the number of clock cycles required for the execution of each external access by the processor forinstruction and data without changing the existing functionality of the processor. This optimization aims to enhance the performance of the existing processor core in a step wise approach with the objective of providing single cycle access for the high speed external interfaces which have less than single cycle access times.

ACHIEVEMENTS

A paper titled “Analysis of Wi-Fi used in UAV” was published in International Journal of Engineering Research & Technology (IJERT), Volume. 3, Issue.11, November – 2014.

A paper titled “Optimization and verification of Bus Interface Unit (BIU) of the in-house developed 32-bit RISC processor core to increase performance” was published in International Journal of Innovative Research in Technology (IJIRT), Volume.1, Issue. 12 May 2015.

Certified training on circuit simulation and PCB designing in Cadence Orcad Tool.

Project is awarded as one of the best project in project exhibition EXPO-2013.

PERSONAL DETAILS

Name : LEEMA RACHEL MATHEW

Date of Birth : 03-11-1991

Postal address : LijoyBhavan, Konalu P O, Nellyady Via

Putturtq- 574229

Dakshina Kannada, Karnataka

Languages Known : English, Hindi, Kannada, and Malayalam

DECLARATION

I do hereby declare that all the above given particulars are true to the best of my knowledge and can produce the testimonials as and when required. Thanking you.

PLACE : Bangalore

DATE : LEEMA RACHEL MATHEW

Contact this candidate