Parikshit Deshpande

**** * ******* *****, *****: 562-***-****

Apt 138, Long Beach, CA 90815 Email: acuhnm@r.postjobfree.com

Objective

Seeking a challenging entry level position that utilizes and enhances my skills in IC layout, ESD/latch up, RTL/DV, IP level DV/Implementation and memory LVS troubleshooting and debug skills.

Technical Skills

Key skills: ASIC/SoC Flow, RTL Design, Synthesis and Verification, Place and Route, Timing analysis, Design of CPU architecture, DDR3, AMBA AHB & APB, FIFO Design, Floating point ASIC design, UVM, Shell & Perl scripting.

Tools: Behavioral Simulation - Synopsys VCS, NCVerilog, Icarus Verilog, ModelSim, Canalyzer.

Synthesis - Synopsys Design Compiler

Gate Level Simulation - NCSim

FPGA tools - Xilinx ISE and Vivado, Altera Quartus II

Place & Route - Cadence Encounter

Programming Languages: Verilog, SystemVerilog, C++, C, VHDL.

Educational Background

M.S in Electrical Engineering at California State University, Long Beach GPA 3.7 May 2016.

Bachelors in Engineering from Nagpur University, India GPA 3.5 May 2012.

Relevant Coursework

VLSI Design, Microelectronics, Mixed Signal IC Design, Computer Communication Networks, Advanced Microprocessors

& Embedded Systems, Memory Design Implementation, CMOS Design, C Programming and Electronic System Design.

Professional Experience

Design Verification Engineer at Sphura Electronics, May 13 - July 14

Functional Verification with RTL and Gate level Simulations.

Generate and Enhance SystemVerilog and verilog Testbench and testcases.

UVM implementation for next gen ASIC

Regression Analysis for design and assertion failures.

Code Coverage Analysis: Analyzed code coverage using Cadence IMC and increased to targeted code coverage.

Implementation of LSF tool and shell scripting for RTL regression testcase simulations.

Post-Si Validation: Hands on debug and probing on chip and complete system PCB.

Design Verification Engineer at Virtual Galaxy InfoTech Pvt Ltd, Nov 12 - May 13

RTL CPU design for next gen Mixed signal SoC.

Functional Verification via Behavioral and Gate level simulation.

Logic Synthesis using Synopsis Design Compiler.

Generate Update and enhance new and existing SystemVerilog testcases.

Regression Analysis for design and assertion failures.

Code coverage using Incisive Metrics Center.

Post-Si Validation.

Academic Projects

1. “Design of Low Power Asynchronous Viterbi Decoder for Wireless Communication”, The objective of this project is to reduce the dynamic power utilization below 10 mW. Asynchronous method is used to communicate between different blocks. Xilinx-Xpower analyzer tool is utilized to measure power consumption. Tools Used: FPGA, XILINX ISE. Skills used: Verilog

2."Boundary Scan", CSU Long Beach, In this project I analyzed sub blocks and pin sates of Xilinx IC XC6SLX16 on FPGA Spartan6 Board.

3."Vision based Robotic Arm", GHRCE Nagpur, Robotic Arm was playing game of TICK-TAC-TOE with human. We used digital image processing for transmitting status of dual colored LED’s (Green- Human, Red- Robotic Arm). Tools Used: MIC 8051, Wireless camera, DC motors, Robotic arm. Skills used: Assembly Language Programming, Asp.Net, Matlab, DIP.

4.“Vehicle Sensing and Detection”, CSU Long Beach, In this project, we detected presence of vehicle, speed and type. Tools used : MSP420, Magnetic Sensors Skills used: Embedded C, Matlab, Code Composer studio/Energia.

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