LEONARD D. COPE

Middletown, Maryland

301-***-****

acu7hh@r.postjobfree.com

Len Cope’s Five Panel Phased Array Com System for First Responders

RF System Design with an emphasis on RF and Mixed Signal Design

Capabilities:

System Architecture

4.9 GHz 802.11a WI-FI RF Wireless Communication System for First Responders;

WI-FI Commercial Communication Systems

RF and Microwave Phased Array Systems, Cognizant Radios and Antennas

Matlab Simulink, Communications Tool Box

Mathematical Analysis

Antenna Directivity,

Signal to Noise Ratios; Closed Loop System Stability Analysis; Phase Lock Loop Stability RF and Microwave Antenna Phased Array Design and Integration

4.9 GHz Switched-Beam Vivaldi Antenna Array; Vivaldi Antenna Design;

4.9 GHz Microstrip Butler-Matrix Networks to implement Phased Array Antenna Networks

13.6 MHz RFID RF Near-Field Communication Systems

Agilent EEsof EDA Design and LTSPICE Software:

Advanced Design System (2013); EMPro 3D EM Sim Software (2013);

PSPICE Return Loss and Filter Analysis; Network Analyzer S Parameter Measurement

MMIC Amplifiers, LNA, filter, mixer, IF amp, RF switch, synthesizer,

Phase Locked Loop, PLL, VCO, loop filter, ADC;

Design of Balun Transformers

Analog Design

Switching Power Supply Design, Design of Power Inductors

Digital Hardware Design

NSA Type I Software Defined Radio, UAV Secure Radio Communication

Nuclear Survivability (REBA, HEMP, Neutron Beam, & Total Gamma Dose)

SONET Telecommunication Optical Transmit and Receive Lasers and Circuits

Digital Timing Clock Recovery with Phase Lock Loops;

Xilinx Zynq ZC702 and Spartan 3A; MINI PCI Interface; DDR SDRAM

AGILENT ADS and LTSPICE Signal Integrity simulation of high speed signals;

Return Loss Simulation and Measurement; Altium Signal Integrity

Altium Schematic Entry and PCB Design; Cadence Orcad & PADS PCB;

Mechanical Design

Solidworks 2015

Education:

Master of Science, Engineering, Yale University, Yale Fellow

Bachelor of Science, EE; University of Maine, Graduated with Highest Honors; 3.79 GPA

Patents:

Patent No. Description

7,053,756 Facilitating Communication of Data Signals on Electric Power Systems

7,046,124 A Power Line Coupling Device and Method of Using the Same

6,998,962 A Power Line Communication Apparatus and Method of Using the Same

6,982,611 A Power Line Coupling Device and Method of Using the Same

Certificates: DOT, Federal Aviation Authority, Private Pilot, Instrument rating

Clearance: Interim Secret

LEONARD D. COPE

acu7hh@r.postjobfree.com

Page 2

Len’s Phased Array System with Zynq-7000 and Spartan 3A FPGA’s

Employment:

October 2015- Present: RF Design Engineer, Carlton National Resources, Germantown, MD.

RF Design Engineer designing RFID RF Near-Field Communication Systems for communication with an implanted medical device.

March 2011 – September 2015: Principal RF Systems Integration Engineer, Engility Corporation, GS&ES, Washington, DC –

Lead Principal Engineer National Institute of Justice Center of Excellence (NIJ COE) in Washington, DC. Designed and Integrated Public Safety Cognitive Radio Systems. LTE 3GPP; IEEE 802.11 a, b, g, n; 802; 80211.16e WIMAX

Specified innovative Architecture, Designed Schematics, Layouts, Performed Simulations and DVT’s to implement cognizant radios.

Cognizant Radio Digital Logic implemented with Linux MAD-Wifi on Xilinx Zynq ZC702 to control a 4.9 GHz Phased Array Antenna System. Array board incorporates Switched-Beam Phased Vivaldi Antenna Array with a Microstrip Butler Array. PCI bus Control by Spartan 3A FPGA with DDR Memory.

Microwave structures designed with SolidWorks and Tested with Agilent ADS and Agilent Momentum. Rogers Duroid 5880 10 GHz PCB Laminate for Vivaldi Antenna. Rogers RO4350B and RO4450F 40 GHz laminates for Father Card with Xilinx FPGA.

. 40 GHz FCC Part 15 & 68 EMI Testing with A.H. Systems Calibrated Antennas, Spectrum Analyzer, and Power Meter.

August 2008 – November 2010: Principal RF Systems Integration Engineer, Thales Communications, Clarksburg, MD –

Designed and Integrated military, tactical Radios with NSA Type I Encryption Waveform Processor Circuit Card Assembly for the software defined ITT/THALES RT-1523G SINCGARS ASIP-G Man-pack Radio. Mixed Signal Base-Band Communication Circuit Design. Power control for nuclear survivability. Spearheaded the Nuclear-Survivability Testing (REBA, HEMP, Neutron Beam, and Total Gamma Dose) at White Sands Missile Range, New Mexico, at the Survivability, Vulnerability and Assessment Directorate (WSMR SVAD). Identified root cause of radiation radio-failure.

Integrated FAA ATM Waveform Modulator Card, with RF Power Linearization.

October 2004 – July 2008: Principal Hardware Design Engineer, General Dynamics C4 Systems, Columbia, MD

Developed a Design Schedule and Costing. Implemented core technology for Integrated Voice Switches for FAA and U.S.A. MARINE RF Communication Systems. Echo cancellation with NLMS Digital Filters. POTS circuits. Designed Avionics Interfaces per DO-178B.;

LEONARD D. COPE

acu7hh@r.postjobfree.com

Page 3

Employment:

September 2001 – June 2004: Principal RF Engineer, Current Technologies, Germantown, MD.

Invented and patented a new paradigm for Power Line Communications. Created a 15KV Passive Power Line RF Coupler for our Power Line Communications System. Solidworks mechanical CAD and Ansys Electrostatic Finite Element Analysis (FEA). Designed Super Heterodyne Receiver. Characterized receiver chain for Noise Figure. Agilent Genesis used to model and analyze the RF response. Test experience includes 10 KV testing of RF Communication systems at KEMA Power Test at Chalfont, Pennsylvania and onsite testing for FCC and UL compliance at METLABS, Baltimore Maryland.

April 1999 –August 2001: Principal Scientist, Lockheed Martin Global Telecommunications, Clarksburg, MD.

Designed Airborne Satellite Modem. Designed Waveform Processor Boards for satellite-communication. Identified requirements for Astrolink™. Specified ASIC’s. Reed Solomon, Viterbi Convolutional Encoding. Programmed ALTERA 10K100 FPGA's Synopsys Synplify synthesized VHDL. Mentor Graphics ModelSim®.

Dec. 1990 - March 1999: Senior Engineer, JDS Uniphase, Germantown, MD.

Captured critical Telecommunication Market share with state of art 622 MHz SONET OC-12 Card. Designed our Telecommunication SONET OC-12 Transmit & Receive card.

The card utilized discrete SONET OC-12, 622.08 MHz fiber optic laser transmitter, discrete Laser receiver, and discrete RF receiver chain with discrete phase-lock-loop clock recovery circuit.

Specified the SONET OC-12 Gallium Arsenide Vitesse ASIC. Designed, Implemented, and tested BER test set. Verilog HDL Xilinx FPGA Design for TCP/IP Protocol Analyzer. Designed DS3 Jitter Analysis Card.

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