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Engineer Design

Location:
KA, India
Posted:
May 30, 2016

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Resume:

SANTOSH M.S.

Objective

Seeking a challenging position in FPGA Design and/or VLSI design where my skills and experience will greatly enhance the company's success and my personal growth.

Technical Skills

H/W Description Languages: VHDL, Verilog, System Verilog and System Verilog Assertions

Other Languages : Matlab

Simulator: Modelsim, from Mentor Graphics and Isim, Vivado Simulator from Xilinx

Tools Used : Xilinx ISE, Vivado, Modelsim, Galaxy Warp, Lattice Diamond, Matlab and PALASM.

Experience

AutoTEC Systems Pvt. Ltd., B’lore

12/2014 - Present

Engineer

As an Engineer, I’m responsible for designing, developing and testing digital circuits for PAL’s, CPLD’s and FPGA devices. Designed and tested the digital portion of the cards in Avionics and Defense related applications.

Responsibilities:

Responsible for complete cycle from specification through Design development and Testing.

Was responsible to handle Technical discussions at client places in Malaysia, Hyderabad and Bangalore.

Designed and tested 16550D compliant UART: Used this UART core to generate multiple channels in applications like Airbone Encoder and Decoder Unit, Telemetry Unit and 1553b to rs422 converter unit.

Designed and tested an Interface Controller Unit to match the compatibility between SIGMA 95NAA Fictional unit and Airborne Satcom Antenna Assembly (SAAA).

Designed and tested Timing Generator block used in HUD Refresh controller. It is an integral part of Message Symbol Generator Card (MSG Card)

Designed and tested the PAL standard Video Generator. It is an integral part of Color Symbol Generator Card (CSG Card)

MSG card and CSG cards are used in Display Processor (DP) of Su-30, Jaguar Mission Computer (JMC) and Core Avionics Computer (CAC) of Mig-27.

Designed and tested Flash card controller to provide an interface between PCMCIA connector and Flash memory chips.

Designed and tested Multi Channel RS422 to RS232 Switch Circuit using PAL device.

Graphene Semiconductor Services Pvt. Ltd., B’lore

2013 - 2014

Project Trainee

As a Trainee, was responsible to work with a team of 11 verification engineers to verify LPDDR2 Memory controller.

Responsibilities:

Responsible for Assertion based verification (ABV) of LPDDR2 Memory interface which was in turn used in LPDDR2 memory controller. System Verilog Assertion language was used to verify the design using Questa Sim simulator.

Designed a verification strategy to test LPDDR2 Memory interface using Assertion based verification methodology. Also derived unique benefits of ABV.

Designed and tested an Arbiter control logic which was used to arbitrate between 32 masters based on an algorithm.

Academic Credentials

M-TECH in VLSI Design and Embedded Systems from BNM Institute of Technology, Banashankari 2nd stage, Bangalore (2012-2014): Secured an aggregate of 75.31% aggregate.

BE in Telecommunication from AMC Engineering College, Bannerghatta Road, Bangalore (2012): Secured an aggregate of 69.32%.

Pre-University Course (Physics, Chemistry, Mathematics and Electronics) from BHS FIRST GRADE COLLEGE, Jayanagar, Bangalore (2008): Secured 75.66%.

SSLC from THE BANGALORE HIGHER SECONDARY SCHOOL, RV Road Basavanagudi Bangalore (2006): Secured 77.28%.

M-Tech Projects

(2013-2014) Assertion based verification(ABV) of LPDDR2 memory interface

(2013)Implementation of Iterative Composite Encryption Algorithm based on TEA and Elgamal

(2012)Implementation of Dragon Cache Coherence Protocol

BE Projects

(2012)Multi-format Data Analysis

(2012)Remote Monitoring and Fire Fighting Robot

Awards and Achievements

Presented a paper titled Assertion Based Verification of LPDDR2 Memory Interface in National Conference-“VCCN-2” held on 9th May 2014 at AMC Engineering College.

Participated in a five day TEQUIP-II INITIATIVE Workshop on Real Time Embedded System Design at R V College of Engineering, Bangalore

Participated in a two day National Workshop on System on Chip(SoC) – Components and Architectures at Reva Institute of Technology, Bangalore

Personal Details

Father’s Name : SHANKAR M.B.

Date of birth : 19th January1991.

Languages Known : English, Hindi, Kannada and Telugu.

Hobbies : Mountaineering and Social Service.



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