KRUTHI H L

M R Residency, Bank Of Baroda Colony, JP Nagar 7th phase, Bangalore

Contact: +91-948*******; Email: actgzj@r.postjobfree.com

ASPIRING VLSI PROFESSIONAL

To obtain an Entry level position as an VERIFICATION Engineer in a VLSI organization which would help me to utilize my academic background that assist me to gain experience, employ my excellent interpersonal skills, and enable me to make a positive contribution to the organization.

SUMMARY OF SKILLS

Qualified B.E. (Electronics & Communication) from P.A College of Engineering (VTU); Pursued RTL DESIGN VERIFICATION BY SV AND UVM course.

Possess comprehensive knowledge & hands on experience in Verilog HDL, System Verilog, UVM Basics

Good understanding in developing Verification Environment from Specification

Good understanding of Code coverage & Functional Coverage .

Strong communication and presentation skills with the ability to perform above expectations.

TECHNICAL SKILLS

Hardware Description Language: Verilog HDL, System Verilog, UVM Basics

Protocol Knowledge: AMBA-APB

EDA Tools Used: QuestaSim, Modelsim

Operating systems: Linux

EDUCATIONAL CREDENTIALS

B.E. (Electronics & Communication), 2012

P.A College of Engineering (VTU); 70%

Diploma in Electronics & Communication, 2009

Board of Technical Education, Sahyadri; 77%

Matriculation, 2004

Junior College (Karnataka Secondary Education Board); 63.36%)

RELEVANT EXPERIENCE AND PROJECTS

Interfacing Keyboard with the FPGA :- Implemented a working design of the system in VHDL and verified the same with random constrained testbenches using Modelsim. describes the basic behavior of a PC keyboard and how to interface it with the FPGA

Arithmetic Logic Unit (ALU):- Implemented a working design of the system in VHDL and verified the same with random constrained testbenches using Modelsim. The ALU takes in user inputs from on-board push buttons and switches, performs selected operations such as addition and subtraction, and shows final results on a 7-segment display.

ACADEMIC PROJECT UNDER TAKEN

Title

New High Speed CMOS Full Adder Cell of Mirror Design Style

Technology used

Cadence Software gpdk180

Role

Layout and Testing

Description

A new circuit of a high-speed CMOS full adder cell provides a higher speed of carry signal formation as compared to the known adders and, hence allows achieving high speed of the N-bit adder device.

Title

GSM based Patient Monitoring System

Technology used

Microcontroller, Wireless Communication

Role

Circuit Designing, developing and testing

Description

Developed a GSM based patient monitoring system that is portable, wireless, personal and suitable for monitoring the patient’s condition

ExTRA CURRICULAR ACCOLADES

Volunteered in ISTE Group held Project meet

Proactively participated in State Level Project Competition

Participated in Sports Meet

PERSONAL DOSSIER

Date of Birth: 19th December 1988

Languages known: English, Hindi and Kannada

Hobbies: Badminton, Crafting and Pencil Drawing

References: Available on request

DATE :-

PLACE: - Bangalore KRUTHI H. L.

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