RESUME

R.Mallikarjun Raju

Email Id: actftl@r.postjobfree.com +919*********

CAREER OBJECTIVE

To be a part of an organization where I can enhance my skills and can put efforts for the company’s growth.

CORE KNOWLEDGE

Good knowledge of Verilog RTL coding, Digital Design Concepts.

Good understanding of fundamentals of Transistors and circuit theory.

Good knowledge of ASIC and FPGA design flow.

Proficient with hands on experience in Digital Design with Verilog, Development of Verification Environment & Constraint Random Test Generation in System Verilog and UVM.

EDUCATIONAL QUALIFICATIONS

DEGREE/

EXAMINATION

SCHOOL/COLLEGE

BOARD/

UNIVERSITY

YEAR OF PASSING

% MARKS

M.Tech

(VLSI System

Design)

VNR Vignana Jyothi Institute Of Technology

JNTU-Hyderabad

2015

79.8

B.Tech (ECE)

S S Institute of Technology

JNTU - Hyderabad

2013

78

Intermediate

(MPC)

Gautami Academy Junior College

Board Of Intermediate, A.P.

2009

89

CLASS X (SSC)

Patmos High School

Board Of Secondary Education, A.P.

2007

82.5

TOOLS &TECHNICAL SKILLS:

ProgrammingLanguages : C,C++

HDLs : Verilog

HVL : System Verilog, UVM

EDA Tools : Xilinx ISE, Modelsim, Questasim-Verification

Platform, Rivera Pro

Operating Systems : Windows XP, Windows 10, Linux

ACTIVITIES & ACHIEVEMENTS

Qualified in PGECET -2013 with 93.66 percentile.

Organized and participated in the Technical Fest in our college in 2013.

Active member of NSS and Blood donation camp.

Stood as winner in Chess at our school level.

VLSI PROJECTS:

DESIGN & VERIFICATION OF ROUTER 1X3

Duration: 1month

HDL :Verilog HDL

HVL : System Verilog

Methodology :UVM

Tools Used :Xilinx ISE, Questasim& Rivera Pro.

Description :Router is a device that forwards data packets between computer networks. It is an OSI Layer3 routing device. Based on a predefined protocol,This router drives an incoming packet to any one among the three outpu channels based on the address field contained in the Packet header.

.

Responsibilities :

Designed RTL using Verilog.

Developed Architecture of Verification Environment using SV & UVM.

Developed of various test cases & verified RTL.

Generated Functional & Code Coverage for Verification Signoff

ACADEMIC PROJECTS:

Title: “Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)”

Role Played: design.

Tools Used :Mentor Graphics Design Architect and IC For Layout and Synopsys.

Description: To design Hetero tunneling transistors and do the low power circuit analysis

Title: “Vedic Multiplier”

Role Played: design.

Tools Used :Modelsim and Xilinx ISE

Description: To design RTL for vedic multiplier in verilog HDL and Functional

verification is done.

Title: “Parallel adder with accumulator”

Role :Schematic and layout design

Tools Used:Mentor Graphics Design Architect and IC For Layout.

Description: To draw Schematic and Layout for parallel adder and performing

DRC and LVS.

AREAS OF INTEREST:

VLSI Design

Communication

Digital Electronics

PERSONAL DETAILS

Name : R. Mallikarjun Raju.

Date of Birth :29 th Oct 1991.

Nationality : Indian.

Languages known : Hindi, Telugu, English.

Father’s Name : R. Krishna.

Address : H.No:13-4-61, V Rama Rao Nagar,

Mothinagar, RR dist, Telangana-500018.

DECLARATION:

I hereby declare that the above mentioned information is correct up to my knowledge and I bear all responsibility for the correctness of the above mentioned particulars.

Place: Hyderabad. [R.Mallikarjun Raju]

Date:

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