Suman Sunkari

Mobile: +91-973******* #*** **th Main, Sector-4,

Email :actf4k@r.postjobfree.com HSR Layout,Bangalore.

CAREER OBJECTIVE:

Seeking a good career where my technical knowledge and analytical skills will be utilized for the growth of the organization in addition to providing me a good learning opportunity.

WORK EXPERIENCE:

Working as an“ASIC Verification Engineer” in “Orange Semiconductors” for client “SanDisk”, Bangalore since 2015.

PROFESSIONAL SUMMARY:

Having 1.6 years of experience in Verification Domain.

Good understanding of ASIC verification flow.

Good programming skills in System Verilog and Verilog Hardware Description Language.

Good understanding and programming skills using Verification methodologies UVM.

Good understanding of scripting languages (PERL, TCL/TK).

Hands on experience with EDA tools (Cadence,Mentor graphics).

Developed GUI for ARC processor in cadence simvision using tcl/tk.

Good Understanding of HVL concepts. Able to code test scenario using existing given test plan. Knowledge of HVL test bench components, debugging HVL environment.

Understanding of assertions, functional coverage metric and identification of additional scenarios.

Experience of developing the verification environment using System Verilog and UVM.

I have knowledge on the APB and AHB protocols.

TECHNICAL SKILLS:

Category

Tools/Languages

HDL programming

Verilog.

HVL Programming

System Verilog Assertions, SV.

Methodologies

UVM.

Scripting languages

Perl, Tcl/Tk

Protocols

APB.

EDA Tools

Cadence Ncsim, Mentor graphics (Questa sim).

Operating system

Linux, Windows.

PROJECTS:

1. Verification of “UART (Universal Asynchronous Receiver & Transmitter)” protocol using “UVM-SV”

Tools Used : Questasim.

Language Used:Verilog/System Verilog and UVM.

Role : Verification Engineer

Description:

UART is a popular serial asynchronous communication to connect the processor and a peripheral. It essentially consists of transmitter and receiver and interrupt controller. Transmitter generates the Uart frame and sends the serial data with baud rate of maximum 3Mbps. Receiver also have 256 byte deep fifo of each 8 bit wide and generates the interrupts to the processor as and when the data is ready in FIFO and also when it receives errors.

Responsibilities:

Developed UVM Test bench.

Written the test cases.

Implemented the Functional Coverage which validates the protocol.

2.Developed the “GUI” for ARC processor using “TCL/TK”.

Tools Used : Cadence Ncsim.

Language Used: TCL/TK.

Description:

Developed the GUI for ARC processor in cadence simvision waveform window using TCL script, to track the pc values and corresponding instruction based on the simvision timestamp.

Responsibilities:

Written the script for GUI and understand the arc related functionality

3.Automation scripts to reduce human effort using“PERL”.

4. Functional coverage on“Memory Controller”

Tools Used : Cadence Ncsim.

Language Used : System Verilog.

Role : Verification Engineer.

Responsibilities:

Written functional coverage based on System Verilog Assertions and properties which validate the protocol, I have written test cases in C/Verilog.

5. Verification of “AMBA APB”

Tools Used : Questasim.

Language Used: verilog/System Verilog.

Role : Verification Engineer

Description:

The APB is part of the AMBA protocol family. It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface.

Responsibilities:

Involved in building the verification environment.

Written the test cases using UVM methodology.

Implemented the Functional Coverage and Assertions which validates the protocol.

6. Verification of “Asynchronous FIFO Verification”

Tools Used : Questasim.

Language Used: Verilog/System Verilog and UVM.

Role : Verification Engineer.

Description:

Designed a 32 x 8bit FIFO with control logic to synchronize cross clock data transfers. Read/Write operate is controlled via individual pointers

Developed a test bench to verify FIFO operation for FIFO Full, FIFO Empty and Random Read/Write data patterns.

Responsibilities:

Involved in building the verification environment.

Written the test cases.

Implemented the Functional Coverage and Assertion which validates the protocol.

EDUCATION:

No

Degree

Passed Out Year

Percentage

Board/University

1

B.Tech

(Electronics & Communication Engg)

April 2013

73.13%

JNTU-H

2

Intermediate(10+2)

April 2009

90.7%

Board Of

Intermediate.

3

S.S.C (10th )

March 2007

81.5%

Board Of Secondary Education.

ACHIEVEMENTS:

I got the first prize in SSC standard.

PROFILE & STRENGTHS:

Qualified B.Tech with excellent technical proficiency and demonstrated analytical abilities and creativity.

PERSONAL DETAILS:

Name : Suman Sunkari

Father’s Name : Laxmaiah

Date of Birth : 06/11/1991

Gender : Male

Languages Known : English, and Telugu

DECLARATION:

I hereby declare that the above-mentioned details are true to my knowledge and I assure you that I would work to my level best if I were selected in your company.

PLACE: Bangalore

DATE: Suman Sunkari

Contact this candidate