Avinash kumar pandey Email : actf2r@r.postjobfree.com

H.No F47,katwaria sarai phone : +91-783*******

South delhi,Pin:110016

Career Objective

Seeking a challenging and rewarding opportunity with an organisation of repute which recognizes my true potential and effectively nurtures my analytical and technical skills EDUCATION

TECHNICAL SKILLS

Programming Language

HDL

C, C++

Verilog

HVL

TB Methodology

System Verilog

UVM Basics

EDA Tools Xilinx ISE design suite, ModelSim,(VCS From EDA playground Scripting Linux (Shell Scripting)

Protocols Knowledge AHB

TRAININGS

o Certification course on VLSI Design and Verification from 3ST Technologies Pvt. Ltd. (Noida) o 6 weeks summer training in optical fibre from BSNL. PUBLICATION

“ 3D NOC implementation using asymmetric torus networks” poster presented in IISF 2015 held at IIT Delhi. WORK EXPERIENCE

o Company : Bright point India pvt ltd.

o Duration : 6 months(From 8

th

April 2013 to 24

th

Sep 2013)

o My role was to find issues in PCB by analysing its circuit. I worked on Printed circuit board (PCB) of various models of Micromax cell phone .

PROJECTS UNDERTAKEN

Project 1- Design of AMBA-AHB protocol using Verilog HDL o AMBA AHB is for high-performance, high clock frequency system modules o Major blocks are advanced peripheral Bridge, AHB Arbiter, AHB master,AHB slave o AHB arbiter decides which master will be active

o Project is modelled in Verilog, simulated in ModelSim 6.4a Project 2- 3D NOC implementation using torus network o Designed two 3-D asymmetric torus networks and connected them by using wrap around edges o Implementation is based on quadrant based XYZ routing algorithm. o Design achieved higher operating frequency as compare to mesh 3-D NOC network. Project 3- Verification environment of no of 1’s counter using system verilog o Designed components driver, generator, monitor scoreboard, agent. o Connected them via mailbox and interfaces, formed verification environment. o Used Functional coverage for verification.

YEAR DEGREE INSTITUTE

PERCENTAGE

2013-15 MTECH (VLSI DESIGN) Galgotias University 64 2008-12 BTECH(ECE) Dr. M.G.R. University 76

2006-08 12th Ranchi college 71

2005-06 10th SNVG 80

Project 4 - Wireless sensor network for precise agriculture monitoring o Designed intelligent system to monitor agricultural environment of crops. o From this we can monitor via wireless sensor network o Language of implementation : mat lab,Embedded

Minor 5- Implemented on FPGA (Spartan 3E)

o Word scrolling on 7-segment display

o Keyboard interfacing

o FIFO

o Digital clock

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