Versha Gedam

Shri Sai Balaji PG,#**,**th Main *nd Cross,

Dollars Scheme, SilkBoard,BTM Mail acteg4@r.postjobfree.com 1st Stage, Bangalore – 560068 Mobile No.- 973-***-**** Statement Of Interests

To pursue a career in Research/Design wherein I can use and acquire my knowledge to contribute for extensive work, organization goals and achieve set targets in the field of VLSI and to look for and work on such assignments which will nourish my academic aptitude and behavioral attitude.

Summary of Qualifications

2.1 Years of experience as a Design and Verification Engineer.

Understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog.

Hands on experience on preparing verification plans, developing UVM and SV based test benches.

Working experience in Linux Environment.

Good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front end design and verification

Experience in working on I2C, AXI, AHB, UART.

Working Experience

Organization: SION Semiconductors Pvt. Ltd. (www.sionsemi.com) Experience: Working with SION Semiconductors as a Design and Verification Trainee Duration: From Jan - 2014 to till date

College: MBITM Dongargarh

Experience: Worked as an Assistant Lecturer

Duration: From Oct-2010 to Apr-2012

VLSI Domain Skills

Educational Qualification

Post Graduation: Master of Technology in VLSI Design. Course School/College Board/University Year Percentag e/CPI

HDLs: Verilog and VHDL

HVL:

Scripting Language:

System Verilog.

Perl

Methodologies: UVM, Coverage Driven Verification, Assertion Based Verification EDA Tool: QuestaSim, Modelsim and Xilinx ISE, Lattice Diamond Domain Knowledge: ASIC/FPGA Design Flow, Digital Design methodologies, RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Image Processing

M.Tech Vishvesvaraya National

Institute of Technology,

Nagpur

Vishvesvaraya National

Institute of Technology,

Nagpur

2012-2014

7.35

B.E. Chhattisgarh Institute of

Technology

Chhattisgarh swami

Vivekanand Technical

University,Bhilai

2006 -

2010

7.40

12th Senior Secondary School

Sec-6, Bhilai

C.B.S.E BOARD 2006 69%

10th Senior Secondary School

Sec-6, Bhilai

C.B.S.E BOARD 2004 70%

VLSI Projects

Advanced High Performance Bus (AHB) Protocol

TestBench Methodology : UVM

HVL: System Verilog

EDA Tools: ModelSim, QuestaSim

Description: AHB is the ARM proprietary protocol. It was designed to Connects multiple masters to multiple slave. It is a single channel interface. It has mainly 4 components Master, Slave, Arbiter and Decoder. Master initiates the transaction, upto 16 Masters are supported on a single AHB. Slave respond to the Master’s request, upto 16 Slaves are supported on a single AHB. Arbiter gives the ownership of the Bus to the highest priority Master. Arbitrer can use any arbitration scheme such as round robin or priority based or any other scheme according to the requirements of the system. A Decoder takes Address, Control and Write Data from each Master and routes the lines from the selected Master it to a common bus that connects to each slave. Similarly, Read Data and Status signals from each Slave are connected to the decoder that routes them from selected slave to a central bus that connects to all Masters. It has transactions in 3 phases i.e. Arbitration, Request and Data phase. For the Verification of Slave the TestBench Environment is developed using Universal Verification Methodology(UVM) and the HVL used is System Verilog and the tool used is ModelSim and QuestaSim.

Role: Designed the Sequence, Sequencer, Driver, Monitor. Advanced eXtensible Interface(AXI) Protocol

HVL: System Verilog

EDA Tools: ModelSim, QuestaSim

Description: AXI is the On Chip Communication Proocol. It is used to connect multiple Masters to multiple Slave.It has 5 Transaction Channels read address, write address, read data, write data, write response. It has many features i.e. Burst Write and Read Transaction, Out of Transaction, Parallel Read and Write Transaction,Over-Lapped Transaction etc. Verification of AXI protocol has been done using System Verilog, TestBench environment has been developed using SV and the ModelSim and QuestaSim tool has been used for Verification. Role : Designed Transactor, Driver and Monitor.

Design and Verification Dual Port RAM using System Verilog and UVM HVL : System Verilog, UVM

EDA Tools: QuestaSim

Description: Prepared a class based layered test bench environment in System Verilog and UVM to verify Memory for Read, Write and Reset operations in Dual Port RAM using single Interface. Role : Whole Design and it’s Verification using System Verilog and UVM. Inter Integrated Circuit(I2C) Protocol

HDL : Verilog

EDA Tools: ModelSim, Xilinx-ISE

Description: I2C is typically used for attaching lower-speed peripheral ICs to processors and microcontrollers.I C uses only two bidirectional open-drain lines, Serial Data Line (SDA) and Serial Clock Line (SCL), pulled up withresistors. Typical voltages used are +5 V or +3.3 V although systems with other voltages are permitted.The I C reference design has a 7-bit or a 10-bit (depending on the device used) address space. Common I C bus speeds are the 100 kbit/s standard mode and the 10 kbit/s low-speed mode, but arbitrarily low clock frequencies are also allowed. Recent revisions of I C can host more nodes and run at faster speeds (400 kbit/s Fast mode, 1 Mbit/sFast mode plus or Fm+, and 3.4 Mbit/s High Speed mode). These speeds are more widely used on embedded systems than on PCs. There are also other features, such as 16-bit addressing. We have designed it for 100kbit/s. It has Clock Stretching and Arbitration Features. The DUT is designed using Verilog and tools used are ModelSim and Xilinx ISE.

Role : Designed the Slave using Verilog.

M.Tech Final Year Project:

Fractal Image Compression:

HDL: VHDL

EDA Tools: ModelSim, Xilinx-ISE

Description: Image compression using fractal transform is a promising method which is potentially capable of achieving very high compression ratios. In fractal image compression the encoding step is computationally expensive. We present a technique that reduces computational complexity and hence reducing the encoding time. The fast fractal algorithm is based on self similarity measures and leads to a novel application of the Fast Fourier Transform based cross-correlation. The whole design has been done using VHDL. Matlab is used for converting the Image into Matrix form. It gives the coordinates of RGB plane. The design is synthesized using Xilinx ISE and Simulated using ModelSim. FPGA Implementation of Cross Correlation has been done. Additional Skills

Programming Language : C, C++

Other VLSI Tools : ComSol Multiphysics, Spice, TCad,ELDO. Extra Curricular Activity

Participated in Advance level Robotics workshop.

Participated in COMSOL workshop.

Participated in ADSP short term course.

Active participation in various cultural activities. Declaration

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars. Versha Gedam

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